coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Krishna P Bhat D (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Tim Wawrzynczak, Julius Werner, Sridhar Siricilla. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... Patch Set 14: (9 comments) Patchset: PS11: > Well, what would you prefer: that you make this change now and test it on your hardware, or that I m […] Agreed. File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59685/comment/eefc70c0_9407cd21 PS13, Line 406: __weak bool is_cse_sub_part_update_req(void) > This doesn't seem like a good use case for weak functions (see CB:58934 for some ongoing discussion […] Done https://review.coreboot.org/c/coreboot/+/59685/comment/f8e19b5a_5d4f8c66 PS13, Line 755: static ssize_t rdev_readat_offset(const struct region_device *rd, void *b, size_t offset, > Why are you redefining a well-known existing function with a different name, anyway? All this achiev […] Done https://review.coreboot.org/c/coreboot/+/59685/comment/2f194975_c11d81f9 PS13, Line 833: static const char *get_source_rdev_fmap_name(void) > Get rid of this function. Don't reimplement what vboot and the CBFS core are already doing for you. Done https://review.coreboot.org/c/coreboot/+/59685/comment/8e4708a9_d6d960b9 PS13, Line 854: static bool cse_sub_part_get_source_rdev(struct region_device *rdev, const char *name) > Get rid of this function. The new CBFS API intentionally abstracts away from raw rdevs. […] Done https://review.coreboot.org/c/coreboot/+/59685/comment/4d26e54f_5c4158ab PS13, Line 932: if (!cse_sub_part_get_source_rdev(&source_rdev, name)) > If you want to get the `name` CBFS file from the currently active boot CBFS, just use […] Was about to push this change in a subsequent patch. Making the changes in this patch now. https://review.coreboot.org/c/coreboot/+/59685/comment/b5854614_7ddf7ee5 PS13, Line 936: if (!cse_get_sub_part_fw_version(type, &source_rdev, &source_fw_ver)) > Just pass the `subpart_cbfs_rw` pointer returned from the above in here, and add the appropriate off […] Ack https://review.coreboot.org/c/coreboot/+/59685/comment/bb80f9ad_2704d488 PS13, Line 983: region_device_sz(&source_rdev) > Here you would just use the `size` variable that got filled out above by cbfs_map(). Done https://review.coreboot.org/c/coreboot/+/59685/comment/fd82a35d_1a54d141 PS13, Line 989: rdev_munmap(&source_rdev, subpart_cbfs_rw); > ...and here you would use […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 14 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 04:12:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Krishna P Bhat D (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Krishna P Bhat D. Hello Marx Wang, build bot (Jenkins), Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Nick Vaccaro, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59685 to look at the new patch set (#14). Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... soc/intel/common: Add support for CSE IOM/NPHY sub-parition update This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1.NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2.Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1.coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2.Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1.coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2.Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h A src/soc/intel/common/block/include/intelblocks/cse_layout.h 6 files changed, 469 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59685/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 14 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetley
by Wizard Shen (Code Review) 02 Dec '21

02 Dec '21

Wizard Shen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59544 ) Change subject: mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetley ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59544/comment/340db8c8_f919749c PS3, Line 2: wizard > Please fix your git setup with `git config --global user.name "Wizard Shen"`. Hi Pual, I used this command to modify my git username,I will pay attention to this action in the subsequent code submission process.Thanks for your correction.Can you help me cherry pick this merged code to the Google code branch? This seems to be automatic operation by the robot, but the robot has not been operated it. Thanks for your help, Wizard -- To view, visit https://review.coreboot.org/c/coreboot/+/59544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1682cdafe1b6ed7cc0cf23624f83d2e5bbfb92e Gerrit-Change-Number: 59544 Gerrit-PatchSet: 5 Gerrit-Owner: Wizard Shen <shenhu5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Krystal Han <hanlijing(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 03:41:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Wizard Shen <shenhu5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add Kconfigs for all PCH types
by EricR Lai (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Angel Pons, Usha P, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59804 ) Change subject: soc/intel/alderlake: Add Kconfigs for all PCH types ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Gerrit-Change-Number: 59804 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 03:14:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: remove duplicates
by Kangheui Won (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Bao Zheng, Felix Held. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59581 ) Change subject: amdfwtool: remove duplicates ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59581/comment/488b1b5b_38bdc743 PS1, Line 12: TEST=build guybrush and confirm amdfw and coreboot.rom are identical > I don't think smu firmware makes any difference here since only duplicate entries are removed. (e.g. […] Tested that aleena(stoneyridge chromebook device) boots without AMD_FW_PSP_TRUSTELETS and AMD_FW_PSP_SECURED_DEBUG binaries. -- To view, visit https://review.coreboot.org/c/coreboot/+/59581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b86e24ba1c2769985e2864528e4dfcbf3cccc4b Gerrit-Change-Number: 59581 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Dec 2021 02:31:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Pass reset gpio parameter to BL31
by Rex-BC Chen (Code Review) 02 Dec '21

02 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59824 ) Change subject: mb/google/cherry: Pass reset gpio parameter to BL31 ...................................................................... mb/google/cherry: Pass reset gpio parameter to BL31 To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3188686 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I48d8d004ea92e950d0040a11133c57c121b86af3 --- M src/mainboard/google/corsola/mainboard.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59824/1 diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index d3d55a2..fa4aa18 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -1,11 +1,27 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bl31.h> #include <console/console.h> #include <device/device.h> #include <soc/msdc.h> #include <soc/spm.h> #include <soc/usb.h> +#include "gpio.h" + +#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h> + +static void register_reset_to_bl31(void) +{ + static struct bl_aux_param_gpio param_reset = { + .h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_aux_param(&param_reset.h); +} + static void mainboard_init(struct device *dev) { mtk_msdc_configure_emmc(true); @@ -19,6 +35,8 @@ if (spm_init()) printk(BIOS_ERR, "spm init failed, system suspend may not work\n"); + + register_reset_to_bl31(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/59824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48d8d004ea92e950d0040a11133c57c121b86af3 Gerrit-Change-Number: 59824 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: build in MT8186 ATF
by Rex-BC Chen (Code Review) 02 Dec '21

02 Dec '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59823 ) Change subject: soc/mediatek/mt8186: build in MT8186 ATF ...................................................................... soc/mediatek/mt8186: build in MT8186 ATF Enable configuration to build with MT8186 arm-trusted-firmware drivers. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3189573 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ib23b112a0bf3d056b932a87b86aaff79508ef50c --- M src/soc/mediatek/mt8186/Kconfig M src/soc/mediatek/mt8186/Makefile.inc 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/59823/1 diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index ce915e2..5393baa 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -5,6 +5,7 @@ select ARCH_VERSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index fbde650..7a2f997 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -58,6 +58,8 @@ ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c +BL31_MAKEARGS += PLAT=mt8186 + CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include -- To view, visit https://review.coreboot.org/c/coreboot/+/59823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib23b112a0bf3d056b932a87b86aaff79508ef50c Gerrit-Change-Number: 59823 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Update camera NVM parameters
by Bernardo Perez Priego (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Selma Bensaid, Paul Menzel, Bernardo Perez Priego, Andy Yeh, kiran2.kumar(a)intel.com, ShawnX Tu. Hello build bot (Jenkins), Selma Bensaid, Tim Wawrzynczak, Andy Yeh, kiran2.kumar(a)intel.com, ShawnX Tu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58374 to look at the new patch set (#8). Change subject: mb/google/brya: Update camera NVM parameters ...................................................................... mb/google/brya: Update camera NVM parameters Change HID name from INT3499 to PRP0001 along with size and address width. Size decreased from 10K to 2K, address width decreased from 14 to 8. BUG=b:203014972 Test= Boot board and issue commands: `cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom > ./brya_imx208_eeprom.bin` `hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log` You should see the result in brya_imx208_eeprom_dump.log to be same as module nvm file by vendor provided or meet the Intel nvm calibration format. (e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00) Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/58374/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Gerrit-Change-Number: 58374 Gerrit-PatchSet: 8 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kiran2.kumar(a)intel.com Gerrit-CC: Bernardo Salvador Perez Priego <bernardospp(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Attention: kiran2.kumar(a)intel.com Gerrit-Attention: ShawnX Tu <shawnx.tu(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Add fls() (Find Last Set)
by Yu-Ping Wu (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59738 ) Change subject: lib: Add fls() (Find Last Set) ...................................................................... Patch Set 4: Code-Review+1 (2 comments) File src/commonlib/bsd/include/commonlib/bsd/helpers.h: https://review.coreboot.org/c/coreboot/+/59738/comment/49b8f14a_b837522c PS1, Line 129: ARCH_X86 > I only have the environment for cherry board, and have no idea how to build for x86 platform, could […] So, there are still errors for PS4 (see Jenkins build console): In file included from src/soc/intel/common/block/fast_spi/fast_spi.c:15: src/include/lib.h:57:19: error: conflicting types for 'fls'; have 'int(u32)' {aka 'int(unsigned int)'} 57 | static inline int fls(u32 x) { return 32 - clz(x); } | ^~~ In file included from src/arch/x86/include/arch/romstage.h:8, from src/soc/intel/common/block/fast_spi/fast_spi.c:5: src/include/cpu/x86/mtrr.h:167:28: note: previous definition of 'fls' with type 'unsigned int(unsigned int)' 167 | static inline unsigned int fls(unsigned int x) | ^~~ Following Julius' suggestion to rename to __fls() would probably solve the problem. https://review.coreboot.org/c/coreboot/+/59738/comment/f7bf5449_a674da4f PS1, Line 137: fls > Sure, is there any document can tell how to do the unit tests? See CB:56543 as an example. Tests can be run by make unit-tests -- To view, visit https://review.coreboot.org/c/coreboot/+/59738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 Gerrit-Change-Number: 59738 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 01:46:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc: Add dram information to cbmem
by Felix Singer (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: soc: Add dram information to cbmem ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59195/comment/c5710271_343d5e1d PS6, Line 7: soc soc/qualcomm/common -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 01:20:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021