coreboot-gerrit December 2021

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Change in coreboot[master]: [TEST-ONLY / HACK] Mirror payload in RAM before hashing/decompression
by Werner Zeh (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Julius Werner. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59767 ) Change subject: [TEST-ONLY / HACK] Mirror payload in RAM before hashing/decompression ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: With this patch I get now much better boot times , so it seems to help somehow: (load payload was 9,352,958 just without this patch) 39 entries total: 0:1st timestamp 36,056 11:start of bootblock 46,376 (10,320) 12:end of bootblock 72,085 (25,708) 13:starting to load romstage 72,113 (27) 14:finished loading romstage 88,561 (16,447) 1:start of romstage 88,587 (26) 970:loading FSP-M 112,200 (23,613) 2:before RAM initialization 216,946 (104,745) 950:calling FspMemoryInit 223,282 (6,335) 951:returning from FspMemoryInit 486,663 (263,380) 3:after RAM initialization 494,963 (8,300) 4:end of romstage 513,677 (18,713) 100:start of postcar 524,544 (10,867) 101:end of postcar 524,545 (0) 8:starting to load ramstage 524,768 (222) 15:starting LZMA decompress (ignore for x86) 561,153 (36,385) 16:finished LZMA decompress (ignore for x86) 576,091 (14,938) 9:finished loading ramstage 576,203 (112) 10:start of ramstage 585,969 (9,765) 17:starting LZ4 decompress (ignore for x86) 634,573 (48,604) 18:finished LZ4 decompress (ignore for x86) 634,674 (101) 30:device enumeration 646,907 (12,232) 971:loading FSP-S 653,502 (6,594) 954:calling FspSiliconInit 653,515 (13) 955:returning from FspSiliconInit 688,218 (34,702) 40:device configuration 729,560 (41,341) 956:calling FspNotify(AfterPciEnumeration) 734,554 (4,994) 957:returning from FspNotify(AfterPciEnumeration) 734,810 (255) 50:device enable 734,812 (1) 60:device initialization 774,419 (39,607) 70:device setup done 805,197 (30,777) 75:cbmem post 805,206 (8) 80:write tables 808,436 (3,230) 85:finalize chips 817,048 (8,611) 90:starting to load payload 818,744 (1,696) 958:calling FspNotify(ReadyToBoot) 3,168,059 (2,349,314) 959:returning from FspNotify(ReadyToBoot) 3,168,720 (661) 960:calling FspNotify(EndOfFirmware) 3,168,720 (0) 961:returning from FspNotify(EndOfFirmware) 3,169,604 (883) 99:selfboot jump 3,170,415 (810) I still need to understand what happens there exactly though. -- To view, visit https://review.coreboot.org/c/coreboot/+/59767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9550ad35653f1c949fe1dd83f76142ed3dbad4c Gerrit-Change-Number: 59767 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 06:17:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Krishna P Bhat D (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Tim Wawrzynczak, Julius Werner, Sridhar Siricilla. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... Patch Set 15: (13 comments) File src/soc/intel/alderlake/romstage/romstage.c: PS14: > Separate CL to enable this for ADL please Done https://review.coreboot.org/c/coreboot/+/59685/comment/d96b9fff_c448ee69 PS14, Line 29: /* If SOC is not Alderlake A2, skip update */ : if (cpu_get_cpuid() != CPUID_ALDERLAKE_A2) { : printk(BIOS_INFO, "CSE Sub-partition update not required\n"); : return true; : } : return false; > I would rather keep the print in common code, and then this function just becomes: […] Done File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59685/comment/6a6f4d70_8bdd8aca PS11, Line 888: cbfs_locate_file_in_region > Looks like this API is getting deprecated. […] Done https://review.coreboot.org/c/coreboot/+/59685/comment/89f092bb_de0a032e PS11, Line 1035: void cse_fw_sync(void) > cse_fw_sync() is being called from SoC romstage.c, but getting enabled from mainboard Kconfig. […] Done File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59685/comment/1d235717_56698a8a PS14, Line 743: uint16_t > `enum bpdt_entry_type` Done https://review.coreboot.org/c/coreboot/+/59685/comment/f5fd219a_68ccc339 PS14, Line 756: uint16_t > `enum bpdt_entry_type ` Done https://review.coreboot.org/c/coreboot/+/59685/comment/133c1f6d_5d521c7a PS14, Line 799: uint16_t > `enum bpdt_entry_type` Done https://review.coreboot.org/c/coreboot/+/59685/comment/f93f02c6_7637b72a PS14, Line 833: ptr + SUBPART_HEADER_SZ > It is technically illegal C to do pointer arithmetic on a `void *`, but GCC does allow it (and proba […] Done https://review.coreboot.org/c/coreboot/+/59685/comment/0279c4bc_8f2a163c PS14, Line 855: uint16_t > `enum bpdt_entry_type` Done https://review.coreboot.org/c/coreboot/+/59685/comment/9da8165c_872f36c7 PS14, Line 913: > nit: extra blank line Done https://review.coreboot.org/c/coreboot/+/59685/comment/21f9442a_a95d6ad4 PS14, Line 997: /* : * If system is in recovery mode, don't trigger recovery again */ > nit: single-line comment Done https://review.coreboot.org/c/coreboot/+/59685/comment/a86f3eab_8af8166d PS14, Line 1018: > nit: extra space Done https://review.coreboot.org/c/coreboot/+/59685/comment/74e7a219_0a0183cd PS14, Line 1020: return; > nit: blank line after `}` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 15 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 05:38:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add override skip_cse_sub_part_update() for alde...
by Krishna P Bhat D (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59826 ) Change subject: soc/intel/alderlake: Add override skip_cse_sub_part_update() for alderlake ...................................................................... soc/intel/alderlake: Add override skip_cse_sub_part_update() for alderlake Check the Alderlake CPU ID to determine if cse sub-paritition update is required or not. Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/59826/1 diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index d33d21f..b9d08c8 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -15,6 +15,7 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <cpu/intel/cpu_ids.h> #include <string.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ @@ -23,6 +24,11 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } +bool skip_cse_sub_part_update(void) +{ + return cpu_get_cpuid() != CPUID_ALDERLAKE_A2; +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Gerrit-Change-Number: 59826 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Krishna P Bhat D (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Julius Werner, Sridhar Siricilla, Krishna P Bhat D. Hello Marx Wang, build bot (Jenkins), Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Nick Vaccaro, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59685 to look at the new patch set (#15). Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... soc/intel/common: Add support for CSE IOM/NPHY sub-parition update This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1.NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2.Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1.coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2.Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1.coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2.Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h A src/soc/intel/common/block/include/intelblocks/cse_layout.h 5 files changed, 460 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59685/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 15 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] drivers/intel/fsp2_0: Add FSP 2.3 support
by Anil Kumar K (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Paul Menzel, Subrata Banik, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59324 to look at the new patch set (#13). Change subject: [WIP] drivers/intel/fsp2_0: Add FSP 2.3 support ...................................................................... [WIP] drivers/intel/fsp2_0: Add FSP 2.3 support - Add Kconfig option - Update FSP build binary version info based on ExtendedImageRevision field in header - New NV HOB related changes will be pushed as part of another patch Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/header_display.c M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/util.c 5 files changed, 39 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59324/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/59324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1 Gerrit-Change-Number: 59324 Gerrit-PatchSet: 13 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_...
by Anil Kumar K (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 ...................................................................... Patch Set 17: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59638/comment/69eed73e_a990aa97 PS15, Line 7: src/ > Please remove. Ack https://review.coreboot.org/c/coreboot/+/59638/comment/86b21c94_30e32523 PS15, Line 7: [WIP] src/drivers/intel/fsp2_0: Update GUID for FSP_NON_VOLATILE_STORAGE_HOB2 HOB : introduced in FSP 2.3 > The commit message summary should be short and fit in one line [1]. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 17 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 04:57:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_...
by Anil Kumar K (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59638 to look at the new patch set (#17). Change subject: [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 ...................................................................... [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e --- M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/include/fsp/util.h 2 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59638/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 17 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE...
by Anil Kumar K (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Anil Kumar K, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59638 to look at the new patch set (#16). Change subject: [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 ...................................................................... [WIP] drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e --- M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/include/fsp/util.h 2 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59638/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 16 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] src/drivers/intel/fsp2_0: Add FSP 2.3 support
by Anil Kumar K (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Paul Menzel, Subrata Banik, Andrey Petrov, Patrick Rudolph. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59324 ) Change subject: [WIP] src/drivers/intel/fsp2_0: Add FSP 2.3 support ...................................................................... Patch Set 11: (4 comments) File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/59324/comment/2ec3f010_e15dbcb6 PS3, Line 24: : #ifdef CONFIG_PLATFORM_USES_FSP2_3 > Hi Subrata. For the HOB changes please use the new patch :https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/59324/comment/2fde6f2d_b32553ad PS3, Line 318: return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size); > const uint8_t fsp_nv_storage_guid_2[16] = { […] Done File src/drivers/intel/fsp2_0/header_display.c: https://review.coreboot.org/c/coreboot/+/59324/comment/f319d4c1_fac6a4c8 PS3, Line 10: ext_revision.val = 0; > you don't need this the value is expected to be zero when we print this info for FSP 2.2 and earlier. i am setting to zero to ensure this. for FSP 2.3 and later we set the value to ExtendenImageRevision in the next line of code. Sounds good ? https://review.coreboot.org/c/coreboot/+/59324/comment/d742a633_25261279 PS3, Line 14: 6 > worthwhile to make use of a macro for this ? […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1 Gerrit-Change-Number: 59324 Gerrit-PatchSet: 11 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Dec 2021 04:54:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update
by Tim Wawrzynczak (Code Review) 02 Dec '21

02 Dec '21

Attention is currently required from: Julius Werner, Sridhar Siricilla, Krishna P Bhat D. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common: Add support for CSE IOM/NPHY sub-parition update ...................................................................... Patch Set 14: (13 comments) File src/soc/intel/alderlake/romstage/romstage.c: PS14: Separate CL to enable this for ADL please https://review.coreboot.org/c/coreboot/+/59685/comment/56f81a79_647632fe PS14, Line 29: /* If SOC is not Alderlake A2, skip update */ : if (cpu_get_cpuid() != CPUID_ALDERLAKE_A2) { : printk(BIOS_INFO, "CSE Sub-partition update not required\n"); : return true; : } : return false; I would rather keep the print in common code, and then this function just becomes: `return cpu_get_cpuid() != CPUID_ALDERLAKE_A2;` File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/59685/comment/81c32eea_f87d39b8 PS11, Line 110: > These blobs are part of FW_MAIN_A/FW_MAIN_B/COREBOOT, they are verified by vboot. Ah yes I see now. File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59685/comment/34e52af9_5d49fe6f PS11, Line 958: /* Get sub-partition blob's version */ > These blobs are part of FW_MAIN_A/FW_MAIN_B/COREBOOT, they are verified by vboot. Ack File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59685/comment/023c21b5_fae4ae03 PS14, Line 743: uint16_t `enum bpdt_entry_type` https://review.coreboot.org/c/coreboot/+/59685/comment/b13f1f26_cbb681ee PS14, Line 756: uint16_t `enum bpdt_entry_type ` https://review.coreboot.org/c/coreboot/+/59685/comment/8a26bfee_528b90cd PS14, Line 799: uint16_t `enum bpdt_entry_type` https://review.coreboot.org/c/coreboot/+/59685/comment/54b0ccfc_8bba5739 PS14, Line 833: ptr + SUBPART_HEADER_SZ It is technically illegal C to do pointer arithmetic on a `void *`, but GCC does allow it (and probably clang too, I'm not sure). Would prefer if you use `uint8_t *` or `uintptr_t` and then cast to pointer later. https://review.coreboot.org/c/coreboot/+/59685/comment/3995e2b7_1a138785 PS14, Line 855: uint16_t `enum bpdt_entry_type` https://review.coreboot.org/c/coreboot/+/59685/comment/bfc09456_12bfcec5 PS14, Line 913: nit: extra blank line https://review.coreboot.org/c/coreboot/+/59685/comment/dd6c4f63_87213be9 PS14, Line 997: /* : * If system is in recovery mode, don't trigger recovery again */ nit: single-line comment https://review.coreboot.org/c/coreboot/+/59685/comment/2ab1d9fb_e9583b72 PS14, Line 1018: nit: extra space https://review.coreboot.org/c/coreboot/+/59685/comment/20943132_c326b31b PS14, Line 1020: return; nit: blank line after `}` -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 14 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 02 Dec 2021 04:38:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2021