coreboot-gerrit December 2021

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Change in coreboot[master]: src/arch/x86/exit_car: Fix regression on x86_64
by Arthur Heymans (Code Review) 05 Dec '21

05 Dec '21

Attention is currently required from: Patrick Rudolph, Subrata Banik, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59871 ) Change subject: src/arch/x86/exit_car: Fix regression on x86_64 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74591e7753cd9c3c097516430a212d416f53e4d Gerrit-Change-Number: 59871 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Sun, 05 Dec 2021 19:42:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Improve x86_64
by Arthur Heymans (Code Review) 05 Dec '21

05 Dec '21

Attention is currently required from: Patrick Rudolph, Tim Wawrzynczak, Paul Menzel, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56017 ) Change subject: Documentation: Improve x86_64 ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855 Gerrit-Change-Number: 56017 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 05 Dec 2021 19:42:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86/exit_car: Add proper x86_64 code
by Arthur Heymans (Code Review) 05 Dec '21

05 Dec '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59873 ) Change subject: src/arch/x86/exit_car: Add proper x86_64 code ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Notice https://review.coreboot.org/c/coreboot/+/54299 (move most of postcar to C code) -- To view, visit https://review.coreboot.org/c/coreboot/+/59873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42d1086f1220e44076ccf613244fc3c6d804805b Gerrit-Change-Number: 59873 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sun, 05 Dec 2021 19:42:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake:[TEST_ONLY][NOT_FOR_MERGE] Run Mem Controller @ l...
by Sridhar Siricilla (Code Review) 05 Dec '21

05 Dec '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59862 to look at the new patch set (#4). Change subject: soc/intel/alderlake:[TEST_ONLY][NOT_FOR_MERGE] Run Mem Controller @ lowest frequency ...................................................................... soc/intel/alderlake:[TEST_ONLY][NOT_FOR_MERGE] Run Mem Controller @ lowest frequency Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ibbc591aff89e166bf90c0cec8bd308f8ea5a47dd --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59862/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbc591aff89e166bf90c0cec8bd308f8ea5a47dd Gerrit-Change-Number: 59862 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch: Remove stryke mainboard
by 9elements QA (Code Review) 05 Dec '21

05 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59875 ) Change subject: mb/google/hatch: Remove stryke mainboard ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 4 / 3 / 7 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/83465 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83463 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/83462 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/83461 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/83460 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/83459 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/83458 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222 Gerrit-Change-Number: 59875 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Dec 2021 17:23:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch: Remove stryke mainboard
by Patrick Georgi (Code Review) 05 Dec '21

05 Dec '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59875 ) Change subject: mb/google/hatch: Remove stryke mainboard ...................................................................... mb/google/hatch: Remove stryke mainboard The stryke project/mainboard never ended up being built and was cancelled early on, therefore remove it from the tree. Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59875 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name D src/mainboard/google/hatch/variants/stryke/Makefile.inc D src/mainboard/google/hatch/variants/stryke/gpio.c D src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl D src/mainboard/google/hatch/variants/stryke/include/variant/ec.h D src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h D src/mainboard/google/hatch/variants/stryke/overridetree.cb 8 files changed, 0 insertions(+), 360 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index de68d85..f17882e 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -127,7 +127,6 @@ default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF - default "Stryke" if BOARD_GOOGLE_STRYKE default "Wyvern" if BOARD_GOOGLE_WYVERN default "Dooly" if BOARD_GOOGLE_DOOLY default "Ambassador" if BOARD_GOOGLE_AMBASSADOR @@ -162,7 +161,6 @@ default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF - default "stryke" if BOARD_GOOGLE_STRYKE default "wyvern" if BOARD_GOOGLE_WYVERN default "dooly" if BOARD_GOOGLE_DOOLY default "ambassador" if BOARD_GOOGLE_AMBASSADOR diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 59e2b69..fea4068 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -123,10 +123,6 @@ bool "-> Scout" select BOARD_GOOGLE_BASEBOARD_PUFF -config BOARD_GOOGLE_STRYKE - bool "-> Stryke" - select BOARD_GOOGLE_BASEBOARD_HATCH - config BOARD_GOOGLE_WYVERN bool "-> Wyvern (CTL Chromebox CBx2)" select BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/variants/stryke/Makefile.inc b/src/mainboard/google/hatch/variants/stryke/Makefile.inc deleted file mode 100644 index ba66a9a..0000000 --- a/src/mainboard/google/hatch/variants/stryke/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -SPD_SOURCES = 4G_2400 # 0b000 -SPD_SOURCES += empty_ddr4 # 0b001 -SPD_SOURCES += 8G_2400 # 0b010 -SPD_SOURCES += 8G_2666 # 0b011 -SPD_SOURCES += 16G_2400 # 0b100 -SPD_SOURCES += 16G_2666 # 0b101 -SPD_SOURCES += 8G_3200 # 0b110 - -bootblock-y += gpio.c -ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c deleted file mode 100644 index 2734629..0000000 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A22 : NC */ - PAD_NC(GPP_A22, NONE), - /* A23 : NC */ - PAD_NC(GPP_A23, NONE), - /* B20 : NC */ - PAD_NC(GPP_B20, NONE), - /* B21 : NC */ - PAD_NC(GPP_B21, NONE), - /* B22 : NC */ - PAD_NC(GPP_B22, NONE), - /* C11 : NC */ - PAD_NC(GPP_C11, NONE), - /* C12 : NC */ - PAD_NC(GPP_C12, NONE), - /* C15 : WWAN_DPR_SAR_ODL - * - * TODO: Driver doesn't use this pin as of now. In case driver starts - * using this pin, expose this pin to driver. - */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* F1 : NC */ - PAD_NC(GPP_F1, NONE), - /* F3 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_F3, NONE, PLTRST), - /* F10 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_F10, NONE, PLTRST), - /* F11 : NC */ - PAD_NC(GPP_F11, NONE), - /* F20 : NC */ - PAD_NC(GPP_F20, NONE), - /* F21 : NC */ - PAD_NC(GPP_F21, NONE), - /* F22 : NC */ - PAD_NC(GPP_F22, NONE), - /* H3 : SPKR_PA_EN */ - PAD_CFG_GPO(GPP_H3, 0, DEEP), - /* H19 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_H19, NONE, PLTRST), - /* H22 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_H22, NONE, PLTRST), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* - * GPIOs configured before ramstage - * Note: the Hatch platform's romstage will configure - * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins - * as inputs before it reads them, so they are not - * needed in this table. - */ -static const struct pad_config early_gpio_table[] = { - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C8 : UART_PCH_RX_DEBUG_TX */ - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), - /* C9 : UART_PCH_TX_DEBUG_RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), - /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, NONE, PLTRST), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl deleted file mode 100644 index fd3b5cf..0000000 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h deleted file mode 100644 index ce6fbfe..0000000 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h deleted file mode 100644 index be96d95..0000000 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - -#endif diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb deleted file mode 100644 index aa73ab6..0000000 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ /dev/null @@ -1,218 +0,0 @@ -chip soc/intel/cannonlake - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 - register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" #Front Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| GSPI1 | | - #| I2C0 | Touchpad | - #| I2C1 | Touch screen | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, - }" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - device domain 0 on - device pci 02.0 on # Integrated Graphics Device - register "gfx" = "GMA_DEFAULT_PANEL(0)" - end - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.2 on end - end - chip drivers/usb/acpi - # No Type-A Port 1 - device usb 2.3 off end - end - chip drivers/usb/acpi - # Unused - device usb 2.4 off end - end - chip drivers/usb/acpi - # No WWAN - device usb 2.5 off end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end - end - chip drivers/usb/acpi - # Unused - device usb 2.7 off end - end - chip drivers/usb/acpi - # Unused - device usb 2.8 off end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - # No Type-A Port 1 - device usb 3.3 off end - end - chip drivers/usb/acpi - # No WWAN - device usb 3.4 off end - end - chip drivers/usb/acpi - # Unused - device usb 3.5 off end - end - end - end - end # USB xHCI - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" - register "wake" = "GPE0_DW0_21" - register "probed" = "1" - device i2c 15 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "reset_delay_ms" = "100" - register "reset_off_delay_ms" = "5" - register "has_power_resource" = "1" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" - register "stop_off_delay_ms" = "5" - device i2c 49 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1e.3 off end # GSPI #1 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA - end - -end 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222 Gerrit-Change-Number: 59875 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/cbfstool: Ensure that htole32 et al are visible when building
by Patrick Georgi (Code Review) 05 Dec '21

05 Dec '21

Attention is currently required from: Rob Barnes. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59891 ) Change subject: util/cbfstool: Ensure that htole32 et al are visible when building ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Rob: This fixes building chromium:3297615, so we'll need to keep that one out of the CQ until this is in and downstreamed, then get them in together. -- To view, visit https://review.coreboot.org/c/coreboot/+/59891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaee7495b2ae64fdc719ae0879ea95fe7df286212 Gerrit-Change-Number: 59891 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Sun, 05 Dec 2021 13:08:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbfstool: Ensure that htole32 et al are visible when building
by Patrick Georgi (Code Review) 05 Dec '21

05 Dec '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59891 ) Change subject: util/cbfstool: Ensure that htole32 et al are visible when building ...................................................................... util/cbfstool: Ensure that htole32 et al are visible when building endian.h wasn't included (although it probably came in as an indirect include) but in some header sets _XOPEN_SOURCE overrides _DEFAULT_SOURCE whereas the latter is a super set of the former: We should get the same things as with _XOPEN_SOURCE (such as memccpy for which it has been defined) but also extra features like htole32. Change-Id: Iaee7495b2ae64fdc719ae0879ea95fe7df286212 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> --- M util/cbfstool/flashmap/fmap.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/59891/1 diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index c152b0d..cb67b46 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause or GPL-2.0-only */ -#define _XOPEN_SOURCE 700 - #include <ctype.h> +#include <endian.h> #include <stdlib.h> #include <stdio.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/59891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaee7495b2ae64fdc719ae0879ea95fe7df286212 Gerrit-Change-Number: 59891 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile.inc: Ignore IASL's "Missing dependency" warning
by HAOUAS Elyes (Code Review) 05 Dec '21

05 Dec '21

Attention is currently required from: Martin Roth, Paul Menzel. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59880 ) Change subject: Makefile.inc: Ignore IASL's "Missing dependency" warning ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: more work is needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/59880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28b437194f08232727623009372327fec15215dd Gerrit-Change-Number: 59880 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 05 Dec 2021 09:29:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Update acpica from 20210331 to 20210930
by HAOUAS Elyes (Code Review) 05 Dec '21

05 Dec '21

Attention is currently required from: HAOUAS Elyes. Hello Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59174 to look at the new patch set (#5). Change subject: crossgcc: Update acpica from 20210331 to 20210930 ...................................................................... crossgcc: Update acpica from 20210331 to 20210930 Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20210930_iasl.patch D util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20210930.tar.gz.cksum 4 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59174/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37 Gerrit-Change-Number: 59174 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021