coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: driver/i2c: Add sx9360 driver
by SH Kim (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Tim Wawrzynczak, Gwendal Grignou. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59608 ) Change subject: driver/i2c: Add sx9360 driver ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Bugzzy need this coreboot driver and kernel driver as well, can we have implementation status? -- To view, visit https://review.coreboot.org/c/coreboot/+/59608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516 Gerrit-Change-Number: 59608 Gerrit-PatchSet: 3 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 06:03:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: move USB3 HUB reset funtion to bootblock
by Yu-Ping Wu (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60088 ) Change subject: mb/google/corsola: move USB3 HUB reset funtion to bootblock ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92feb2316302fda32478b24c014bcd380d0ac55d Gerrit-Change-Number: 60088 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 05:49:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
by Usha P (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59937 ) Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N ...................................................................... Patch Set 5: (2 comments) File src/mainboard/intel/adlrvp/early_gpio_n.c: https://review.coreboot.org/c/coreboot/+/59937/comment/2fe6c25d_d649a5ad PS4, Line 14: > what about […] Added EC_IN_RW. This platform is MD. https://review.coreboot.org/c/coreboot/+/59937/comment/8afb616d_2f1e49ed PS4, Line 16: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1), : : /* CPU PCIe vGPIO for RP1 */ : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1), : : /* CPU PCIe vGPIO for RP2 */ : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1), : : /* CPU PCIe vGPIO for RP3 */ : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), > Note about these, we have actually found `PLTRST` to be the correct reset type for these PCIe VGPIOs […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Gerrit-Change-Number: 59937 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 05:34:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add Kconfig for Alder Lake-N
by Usha P (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Maulik V Vaghela, Reka Norman, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Krishna P Bhat D, Kangheui Won. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59724 ) Change subject: mb/intel/adlrvp: Add Kconfig for Alder Lake-N ...................................................................... Patch Set 6: (1 comment) File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/59724/comment/56d7c6d4_b4538a73 PS5, Line 97: default "ADLRVPP" > Should this have an entry for "ADLRVPN"? Yes, Thankyou. -- To view, visit https://review.coreboot.org/c/coreboot/+/59724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091663590966c174f980e41a31c93c44c7add529 Gerrit-Change-Number: 59724 Gerrit-PatchSet: 6 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 05:33:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
by Usha P (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Kangheui Won, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Usha P. Hello build bot (Jenkins), Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Reka Norman, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59937 to look at the new patch set (#5). Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N ...................................................................... mb/intel/adlrvp: Configure GPIOs for Alder Lake-N List of changes: 1. Add separate file for ADL-N GPIOs 2. Configure GPIOs as per the schematics of ADL-N RVP Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/early_gpio_n.c A src/mainboard/intel/adlrvp/gpio_n.c 3 files changed, 345 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/59937/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Gerrit-Change-Number: 59937 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Add Kconfig for Alder Lake-N
by Usha P (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Krishna P Bhat D, Usha P, Kangheui Won. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Reka Norman, Rizwan Qureshi, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Krishna P Bhat D, Kangheui Won, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59724 to look at the new patch set (#6). Change subject: mb/intel/adlrvp: Add Kconfig for Alder Lake-N ...................................................................... mb/intel/adlrvp: Add Kconfig for Alder Lake-N This patch includes the following changes 1. Add mainboard Kconfig to Kconfig.name file 2. Handle mainboard names in Kconfig file for ADLRVP N 3. Add config options to pick the adlrvp_n devicetree Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I091663590966c174f980e41a31c93c44c7add529 --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Kconfig.name 2 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59724/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/59724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091663590966c174f980e41a31c93c44c7add529 Gerrit-Change-Number: 59724 Gerrit-PatchSet: 6 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: Create corori2 variant
by Ian Feng (Code Review) 14 Dec '21

14 Dec '21

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60093 ) Change subject: mb/google/dedede: Create corori2 variant ...................................................................... mb/google/dedede: Create corori2 variant Create the corori2 variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:209892078 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CORORI2 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I7bf437aa9ef70e4a470ab9727ee076c251433e01 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/corori2/Makefile.inc A src/mainboard/google/dedede/variants/corori2/gpio.c A src/mainboard/google/dedede/variants/corori2/include/variant/ec.h A src/mainboard/google/dedede/variants/corori2/include/variant/gpio.h A src/mainboard/google/dedede/variants/corori2/memory/Makefile.inc A src/mainboard/google/dedede/variants/corori2/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/corori2/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/corori2/overridetree.cb 10 files changed, 263 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/60093/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 29a9481..31ac491 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -112,6 +112,7 @@ default "Driblee" if BOARD_GOOGLE_DRIBLEE default "Gooey" if BOARD_GOOGLE_GOOEY default "Beadrix" if BOARD_GOOGLE_BEADRIX + default "Corori2" if BOARD_GOOGLE_CORORI2 config MAX_CPUS int @@ -150,6 +151,7 @@ default "driblee" if BOARD_GOOGLE_DRIBLEE default "gooey" if BOARD_GOOGLE_GOOEY default "beadrix" if BOARD_GOOGLE_BEADRIX + default "corori2" if BOARD_GOOGLE_CORORI2 endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 212f242..7e9ffcf 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -175,3 +175,9 @@ bool "-> Beadrix" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_CORORI2 + bool "-> Corori2" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/dedede/variants/corori2/Makefile.inc b/src/mainboard/google/dedede/variants/corori2/Makefile.inc new file mode 100644 index 0000000..eb2c9bc --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori2/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/corori2/gpio.c b/src/mainboard/google/dedede/variants/corori2/gpio.c new file mode 100644 index 0000000..2a615a07d --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori2/gpio.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A11 : TOUCH_RPT_EN ==> NC */ + PAD_NC(GPP_A11, NONE), + /* C12 : AP_PEN_DET_ODL ==> NC */ + PAD_NC(GPP_C12, UP_20K), + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + /* C22 : UART2_RTS_N ==> NC */ + PAD_NC(GPP_C22, UP_20K), + /* D4 : TOUCH_INT_ODL ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D5 : TOUCH_RESET_L ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D12 : WCAM_RST_L ==> NC */ + PAD_NC(GPP_D12, NONE), + /* D14 : EN_PP1200_CAMERA ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 ==> NC */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 ==> NC */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 ==> NC */ + PAD_NC(GPP_D21, NONE), + /* E0 : CLK_24M_UCAM ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E2 : CLK_24M_WCAM ==> NC */ + PAD_NC(GPP_E2, NONE), + /* H1 : EN_PP3300_SD_U ==> NC */ + PAD_NC(GPP_H1, NONE), + /* H4 : AP_I2C_TS_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : AP_I2C_TS_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H6 : AP_I2C_CAM_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* G0 : SD_CMD ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL ==> NC */ + PAD_NC(GPP_G5, UP_20K), + /* G6 : SD_CLK ==> NC */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP ==> NC */ + PAD_NC(GPP_G7, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/corori2/include/variant/ec.h b/src/mainboard/google/dedede/variants/corori2/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori2/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/corori2/include/variant/gpio.h b/src/mainboard/google/dedede/variants/corori2/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori2/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/corori2/memory/Makefile.inc b/src/mainboard/google/dedede/variants/corori2/memory/Makefile.inc new file mode 100644 index 0000000..7758964 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori2/memory/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/corori2/memory src/mainboard/google/dedede/variants/corori2/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/corori2/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/corori2/memory/dram_id.generated.txt new file mode 100644 index 0000000..580dd1c --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori2/memory/dram_id.generated.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/corori2/memory src/mainboard/google/dedede/variants/corori2/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/corori2/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/corori2/memory/mem_parts_used.txt new file mode 100644 index 0000000..ae86d68 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori2/memory/mem_parts_used.txt @@ -0,0 +1,2 @@ +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/corori2/overridetree.cb b/src/mainboard/google/dedede/variants/corori2/overridetree.cb new file mode 100644 index 0000000..71440ab --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori2/overridetree.cb @@ -0,0 +1,147 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # None + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # None + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # None + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera (UFC) + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # None + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # None + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # None + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | | + #| I2C2 | | + #| I2C3 | | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .rise_time_ns = 255, + .fall_time_ns = 14, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + } + }, + }" + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000) + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN) + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + device generic 0 on end + end + end # SA Thermal device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + device usb 2.1 off end + end + chip drivers/usb/acpi + device usb 2.3 off end + end + chip drivers/usb/acpi + register "desc" = ""Camera (UFC)"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 3.1 off end + end + chip drivers/usb/acpi + device usb 3.3 off end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 1c.7 on end + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/60093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bf437aa9ef70e4a470ab9727ee076c251433e01 Gerrit-Change-Number: 60093 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ChromeOS: Refactor ACPI CNVS generation
by Kyösti Mälkki (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55502 ) Change subject: ChromeOS: Refactor ACPI CNVS generation ...................................................................... Patch Set 16: (1 comment) Patchset: PS16: ping -- To view, visit https://review.coreboot.org/c/coreboot/+/55502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Gerrit-Change-Number: 55502 Gerrit-PatchSet: 16 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 14 Dec 2021 04:38:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8
by Kyösti Mälkki (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Dmitry Ponamorev, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, King Sumo. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 ...................................................................... Patch Set 21: (2 comments) File src/mainboard/teleplatforms/D4E4S16P8/Kconfig: https://review.coreboot.org/c/coreboot/+/57194/comment/5411e0ee_ae22d92e PS19, Line 31: default "1.0.12" > Done I meant there is a visible choice in menuconfig named LOCALVERSION. Setting that will be reflected in SMBIOs strings. See patchset #21. File src/mainboard/teleplatforms/D4E4S16P8/romstage.c: https://review.coreboot.org/c/coreboot/+/57194/comment/b2472b9f_df30434d PS20, Line 437: {SOUTH_GROUP0_CTBTRIGINOUT, Except for this, this is all copy-paste from intel/harcuvar. Some like eMMC below seems wrong. Dmitry, would you go thru the list against schematics? -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 21 Gerrit-Owner: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 04:34:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dmitry Ponamorev <dponamorev(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps
by build bot (Jenkins) (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36607 ) Change subject: [WIP] teleplatforms/D4E4S16P8: Configure ast25xx bootstraps ...................................................................... Patch Set 13: (3 comments) File src/mainboard/teleplatforms/D4E4S16P8/ast25xx.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135473): https://review.coreboot.org/c/coreboot/+/36607/comment/de86d00f_8bdfca16 PS13, Line 44: printk(BIOS_INFO, "ast25xx: disable protection status: @ 0x%p 0x%08x\n", scu_protection, locks); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135473): https://review.coreboot.org/c/coreboot/+/36607/comment/68d09b80_0ac5a277 PS13, Line 47: printk(BIOS_INFO, "ast25xx: scu70_hwtrap current bits: @ 0x%p 0x%08x\n", scu_hwtrap, straps); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135473): https://review.coreboot.org/c/coreboot/+/36607/comment/41de6811_289510db PS13, Line 76: printk(BIOS_INFO, "ast25xx: p2p_bridge0: 0x%x; p2p_bridge1: 0x%x\n", p2p_bridge0, p2p_bridge1); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/36607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92195969419f9c38845cb67f294fdab33fb481af Gerrit-Change-Number: 36607 Gerrit-PatchSet: 13 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Guckian <d.guckian20(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 04:29:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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