coreboot-gerrit December 2021

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Change in coreboot[master]: Denverton-NS boards: Factor out common PCI IRQ config
by Angel Pons (Code Review) 14 Dec '21

14 Dec '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60102 ) Change subject: Denverton-NS boards: Factor out common PCI IRQ config ...................................................................... Denverton-NS boards: Factor out common PCI IRQ config Both Denverton-NS mainboards have identical `mainboard_pci_irqs.asl` files, so factor it out. Change-Id: Ib7f15f4781fbef7bee1f0cd40692180ec49acd9f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl R src/soc/intel/denverton_ns/acpi/pci_irqs.asl M src/soc/intel/denverton_ns/acpi/southcluster.asl 3 files changed, 1 insertion(+), 175 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/60102/1 diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl deleted file mode 100644 index 3482e23..0000000 --- a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl +++ /dev/null @@ -1,173 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* This is board specific information: IRQ routing */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // [GREG]: Global Registers - Package() { 0x0004ffff, 0, 0, 16 }, - - // [RCEC]: Root Complex Event Collector - Package() { 0x0005ffff, 0, 0, 23 }, - - // [VRP2]: Virtual root port 2 - Package() { 0x0006ffff, 2, 0, 18 }, - - // [PEX0]: PCI Express Port 0 - Package() { 0x0009ffff, 0, 0, 16 }, - - // [PEX1]: PCI Express Port 1 - Package() { 0x000affff, 1, 0, 17 }, - - // [PEX2]: PCI Express Port 2 - Package() { 0x000bffff, 2, 0, 18 }, - - // [PEX3]: PCI Express Port 3 - Package() { 0x000cffff, 3, 0, 19 }, - - // [PEX4]: PCI Express Port 4 - Package() { 0x000effff, 0, 0, 20 }, - - // [PEX5]: PCI Express Port 5 - Package() { 0x000fffff, 1, 0, 21 }, - - // [PEX6]: PCI Express Port 6 - Package() { 0x0010ffff, 2, 0, 22 }, - - // [PEX7]: PCI Express Port 7 - Package() { 0x0011ffff, 3, 0, 23 }, - - // [SMB1]: SMBus controller - Package() { 0x0012ffff, 0, 0, 16 }, - - // [SAT0]: SATA controller 0 - Package() { 0x0013ffff, 0, 0, 20 }, - - // [SAT1]: SATA controller 1 - Package() { 0x0014ffff, 0, 0, 21 }, - - // [XHC0]: XHCI USB controller - Package() { 0x0015ffff, 0, 0, 19 }, - - // [VRP0]: Virtual root port 0 - Package() { 0x0016ffff, 0, 0, 16 }, - - // [VRP1]: Virtual root port 1 - Package() { 0x0017ffff, 1, 0, 17 }, - - // [HECI]: ME HECI - Package() { 0x0018ffff, 0, 0, 16 }, - - // [HEC2]: ME HECI2 - Package() { 0x0018ffff, 1, 0, 17 }, - - // [MEKT]: MEKT on PCH - Package() { 0x0018ffff, 2, 0, 18 }, - - // [HEC3]: ME HECI3 - Package() { 0x0018ffff, 3, 0, 19 }, - - // [UAR0]: UART 0 - Package() { 0x001affff, 0, 0, 16 }, - - // [UAR1]: UART 1 - Package() { 0x001affff, 1, 0, 17 }, - - // [UAR2]: UART 2 - Package() { 0x001affff, 2, 0, 18 }, - - // [EMMC]: eMMC - Package() { 0x001cffff, 0, 0, 16 }, - - // [P2SB]: Primary to sideband bridge - // [SMB0]: SMBus controller - // [NPK0]: Northpeak DFX - Package() { 0x001fffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // [GREG]: Global Registers 0:4.0 - Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [RCEC]: Root Complex Event Collector 0:5.0 - Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - - // [VRP2]: Virtual root port 2 0:6.0 - Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - - // [PEX0]: PCI Express Port 0 0:9.0 - Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [PEX1]: PCI Express Port 1 0:a.0 - Package() { 0x000affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // [PEX2]: PCI Express Port 2 0:b.0 - Package() { 0x000bffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - - // [PEX3]: PCI Express Port 3 0:c.0 - Package() { 0x000cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - - // [PEX4]: PCI Express Port 4 0:e.0 - Package() { 0x000effff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - - // [PEX5]: PCI Express Port 5 0:f.0 - Package() { 0x000fffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - - // [PEX6]: PCI Express Port 6 0:10.0 - Package() { 0x0010ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, - - // [PEX7]: PCI Express Port 7 0:11.0 - Package() { 0x0011ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, - - // [SMB1]: SMBus controller 0:12.0 - Package() { 0x0012ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [SAT0]: SATA controller 0 0:13.0 - Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - - // [SAT1]: SATA controller 1 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - - // [XHC0]: XHCI USB controller 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - - // [VRP0]: Virtual root port 0 0:16.0 - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [VRP1]: Virtual root port 1 0:17.0 - Package() { 0x0017ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // [HECI]: ME HECI 0:18.0 - Package() { 0x0018ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [HEC2]: ME HECI2 0:18.1 - Package() { 0x0018ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // [MEKT]: MEKT on PCH 0:18.2 - Package() { 0x0018ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - - // [HEC3]: ME HECI3 0:18.3 - Package() { 0x0018ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - - // [UAR0]: UART 0 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [UAR1]: UART 1 0:1a.1 - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // [UAR2]: UART 2 0:1a.2 - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - - // [EMMC]: eMMC 0:1c.0 - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [P2SB]: Primary to sideband bridge - // [SMB0]: SMBus controller - // [NPK0]: Northpeak DFX - Package() { 0x001ffffF, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl b/src/soc/intel/denverton_ns/acpi/pci_irqs.asl similarity index 100% rename from src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl rename to src/soc/intel/denverton_ns/acpi/pci_irqs.asl diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index 72e12bd..a692966 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -122,8 +122,7 @@ // Northpeak 0:1f.7 #include "npk.asl" -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/mainboard_pci_irqs.asl" +#include "pci_irqs.asl" Method (_OSC, 4) { -- To view, visit https://review.coreboot.org/c/coreboot/+/60102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7f15f4781fbef7bee1f0cd40692180ec49acd9f Gerrit-Change-Number: 60102 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Do not trigger crashlog on all resets by default
by Curtis Chen (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Francois Toguo Fotso, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Curtis Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59951 ) Change subject: soc/intel/common: Do not trigger crashlog on all resets by default ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/59951/comment/88efb70a_a6a9945d PS2, Line 332: def_bool n : help : Enable PMC reset crashlog record. > It's followed by the above config SOC_INTEL_CRASHLOG in the same file. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Gerrit-Change-Number: 59951 Gerrit-PatchSet: 3 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 09:55:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Curtis Chen <curtis.chen(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Do not trigger crashlog on all resets by default
by Curtis Chen (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Francois Toguo Fotso, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Hello build bot (Jenkins), Francois Toguo Fotso, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59951 to look at the new patch set (#3). Change subject: soc/intel/common: Do not trigger crashlog on all resets by default ...................................................................... soc/intel/common: Do not trigger crashlog on all resets by default Crashlog has error records and PMC reset records two parts. When we send ipc cmd "PMC_IPC_CMD_ID_CRASHLOG_ON_RESET", PMC reset record is enabled. At each warm/cold/global reset, crashlog would be triggered. The cause of this crash would be "TRIGGER_ON_ALL_RESETS", it is used to catch unknown reset reason. At the same time, we would see [Hardware Error] in the kernel log. If we default enable TRIGGER_ON_ALL_RESETS, we would have too many false alarm. Now we disable PMC reset records part by default. And we could enable it when we need it for the debug purpose. The generated bert dump is under /var/spool/crash/, we could check this path to verify this CONFIG disable/enable status. BUG=b:202737385 TEST=No new bert dump after reset. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/Kconfig.common M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/tigerlake/Kconfig 4 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/59951/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Gerrit-Change-Number: 59951 Gerrit-PatchSet: 3 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8
by Angel Pons (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Dmitry Ponamorev, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph, King Sumo. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 ...................................................................... Patch Set 21: Code-Review+1 (15 comments) File src/mainboard/teleplatforms/D4E4S16P8/Kconfig: https://review.coreboot.org/c/coreboot/+/57194/comment/5dc2d82e_0c73d136 PS21, Line 17: string Not needed since CB:56553 https://review.coreboot.org/c/coreboot/+/57194/comment/75843fb4_7f737f20 PS21, Line 21: string Not needed since CB:56554 https://review.coreboot.org/c/coreboot/+/57194/comment/062583d3_edf7b5f8 PS21, Line 24: config MAINBOARD_VENDOR : string : default "teleplatforms" Already set in `src/mainboard/teleplatforms/Kconfig` File src/mainboard/teleplatforms/D4E4S16P8/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/57194/comment/927b4144_27861e89 PS21, Line 5: Device (PWRB) : { : Name(_HID, EisaId("PNP0C0C")) : : // Wake : Name(_PRW, Package(){0x1d, 0x05}) : } This shouldn't be needed, see CB:27272 File src/mainboard/teleplatforms/D4E4S16P8/acpi/mainboard_pci_irqs.asl: https://review.coreboot.org/c/coreboot/+/57194/comment/07d8f4cb_ab20fbbb PS21, Line 3: board specific Hmmm, doesn't seem to be that board-specific: the other two DNV-NS boards (scaleway/tagada and intel/harcuvar) have the exact same file. File src/mainboard/teleplatforms/D4E4S16P8/acpi/thermal.asl: PS21: If there are no plans to add more stuff here, I'd drop the file. File src/mainboard/teleplatforms/D4E4S16P8/acpi_tables.c: https://review.coreboot.org/c/coreboot/+/57194/comment/e6f90832_756324b7 PS21, Line 13: /* Disable USB ports in S5 */ : gnvs->s5u0 = 0; : gnvs->s5u1 = 0; These values are only used with mainboard-specific SMI handlers and/or ACPI. They are otherwise meaningless and this could be dropped. https://review.coreboot.org/c/coreboot/+/57194/comment/32db178a_0b3195ad PS21, Line 17: /* TPM Present */ : gnvs->tpmp = 0; Doesn't seem to be used anywhere in coreboot. Default is already zero, so I'd drop this. File src/mainboard/teleplatforms/D4E4S16P8/ramstage.c: https://review.coreboot.org/c/coreboot/+/57194/comment/b72e6c7d_7e30ea0c PS21, Line 26: 0x56 EEPROM_ADDR https://review.coreboot.org/c/coreboot/+/57194/comment/2b7b0b9d_caa80b50 PS21, Line 26: SMBUS_IO_BASE Why not `smbus_base()`? https://review.coreboot.org/c/coreboot/+/57194/comment/4fd11e75_825809dc PS21, Line 28: tmp == 0x3f/*?*/ nit: you can use a character literal in the comparison: tmp == `?` https://review.coreboot.org/c/coreboot/+/57194/comment/b82a4521_85210708 PS21, Line 28: (tmp < 0x20 || tmp > 0x7f) 0x7f is DEL, which isn't printable. If you exclude it, the resulting check is the complement (negation) of `isprint()` from `src/include/ctype.h`. https://review.coreboot.org/c/coreboot/+/57194/comment/50107993_dccbb59f PS21, Line 30: memset(serial, 0, sizeof(serial)); : memcpy(serial, ERROR_STRING, sizeof(ERROR_STRING)); : return serial; Why not simply `return ERROR_STRING;` instead? https://review.coreboot.org/c/coreboot/+/57194/comment/034ea3b3_97ec4496 PS21, Line 43: unsigned int smbios_cpu_get_max_speed_mhz(void) : { : return 2400; : } : : unsigned int smbios_cpu_get_current_speed_mhz(void) : { : return 2400; : } Hmmm, Intel says the Atom C3758 has a clock speed of 2200 MHz: https://ark.intel.com/content/www/us/en/ark/products/97926/intel-atom-proce… File src/mainboard/teleplatforms/D4E4S16P8/romstage.c: https://review.coreboot.org/c/coreboot/+/57194/comment/9c08cb8b_6c6d9583 PS20, Line 437: {SOUTH_GROUP0_CTBTRIGINOUT, > Except for this, this is all copy-paste from intel/harcuvar. Some like eMMC below seems wrong. […] Would be interesting to use the coreboot GPIO configuration mechanism instead, which scaleway/tagada uses. IMHO, it's significantly more readable. -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 21 Gerrit-Owner: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 09:51:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus: Update thermal table for primus
by Ariel Fang (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60101 to look at the new patch set (#3). Change subject: mb/google/brya/var/primus: Update thermal table for primus ...................................................................... mb/google/brya/var/primus: Update thermal table for primus - Beause primus have five sensors,we need to define 5 sensors. BUG=b:200836803 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com> Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 16 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/60101/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d Gerrit-Change-Number: 60101 Gerrit-PatchSet: 3 Gerrit-Owner: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation
by Casper Chang (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Malik Hsu, Nick Vaccaro. Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60071 ) Change subject: mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60071/comment/0cde4421_b3430aaa PS1, Line 7: primus > Sometimes we use shell-like glob sequences to indicate we are modifying more than one board, in this […] Done https://review.coreboot.org/c/coreboot/+/60071/comment/4e1989bc_ab863b8b PS1, Line 8: > Maybe mention that this was verified to meet the audible noise specification (or is still in testing […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 Gerrit-Change-Number: 60071 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 09:25:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation
by Casper Chang (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Malik Hsu, Nick Vaccaro, Casper Chang. Hello build bot (Jenkins), Malik Hsu, Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60071 to look at the new patch set (#2). Change subject: mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigation - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 BUG=b:204844399 TEST=USE="project_primus emerge-brya coreboot" and verified the setting meets the audible noise specification Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/60071/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 Gerrit-Change-Number: 60071 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Fix MRC_RW_CACHE
by Angel Pons (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60091 ) Change subject: soc/intel/denverton_ns: Fix MRC_RW_CACHE ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/intel/denverton_ns/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/60091/comment/944300c5_ef0a6cb7 PS1, Line 15: #include <intelblocks/fast_spi.h> Already included on line 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/60091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e Gerrit-Change-Number: 60091 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 09:19:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Use common SMBus support code
by Angel Pons (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59469 ) Change subject: soc/intel/denverton_ns: Use common SMBus support code ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/denverton_ns/include/soc/smbus.h: https://review.coreboot.org/c/coreboot/+/59469/comment/7a28eac2_7bb2879c PS2, Line 20: 0x24 Where does this come from? According to Document 337018-002 (Intel Atom® Processor C3000 Product Family Datasheet), the reset default is 0x44: https://imgur.com/BsnyKJW.png -- To view, visit https://review.coreboot.org/c/coreboot/+/59469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513 Gerrit-Change-Number: 59469 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 09:18:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Use common SMBus support code
by Angel Pons (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59469 ) Change subject: soc/intel/denverton_ns: Use common SMBus support code ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/soc/intel/denverton_ns/Kconfig: https://review.coreboot.org/c/coreboot/+/59469/comment/e1c53cfb_3c62e222 PS2, Line 38: select SOUTHBRIDGE_INTEL_COMMON_SMBUS I wonder if `SOC_INTEL_COMMON_BLOCK_SMBUS` should select `SOUTHBRIDGE_INTEL_COMMON_SMBUS`. Best done in a follow-up. -- To view, visit https://review.coreboot.org/c/coreboot/+/59469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513 Gerrit-Change-Number: 59469 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 09:12:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021