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Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59469
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Change subject: soc/intel/denverton_ns: Use common SMBus support code
......................................................................
soc/intel/denverton_ns: Use common SMBus support code
Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/include/soc/pci_devs.h
M src/soc/intel/denverton_ns/include/soc/smbus.h
4 files changed, 6 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/59469/3
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Kyösti Mälkki has uploaded a new patch set (#11) to the change originally created by Dmitry Ponamorev. ( https://review.coreboot.org/c/coreboot/+/57668 )
Change subject: soc/intel/baytrail,denverton_ns: Call setup_lapic()
......................................................................
soc/intel/baytrail,denverton_ns: Call setup_lapic()
A custom board with soc/intel/denverton_ns does not respond to
the keyboard and does not boot from the sata/USB disks.
Last post code 0x7b and the last line that is displayed at log
from SeaBIOS is:
All threads complete.
The issue is gone when adding setup_lapic() call to configure
EXTINT delivery of i8259 originated interrupts for the LAPIC.
Replicate call from other soc/ and make the call for both BSP
and AP CPUs.
Similar change was done for soc/intel/braswell in
commit b4f57bb3cac3ab29b9fa9c526ad4358faffb77a1.
Signed-off-by: Dmitry Ponamorev <dponamorev(a)gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d
---
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/denverton_ns/cpu.c
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/57668/11
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59724 )
Change subject: mb/intel/adlrvp: Add Kconfig for Alder Lake-N
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Since 59915 is a copy patch for device tree, we wanted to keep Kconfig patch separate.
The problem is that the code from CB:59915 is not build-tested.
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Change subject: mb/intel/adlrvp: Add Kconfig for Alder Lake-N
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Any reason to not include these changes as part of CB:59915 ?
Since 59915 is a copy patch for device tree, we wanted to keep Kconfig patch separate.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59724 )
Change subject: mb/intel/adlrvp: Add Kconfig for Alder Lake-N
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
Any reason to not include these changes as part of CB:59915 ?
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Attention is currently required from: Francois Toguo Fotso, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph.
Hello build bot (Jenkins), Francois Toguo Fotso, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59951
to look at the new patch set (#4).
Change subject: soc/intel/common: Do not trigger crashlog on all resets by default
......................................................................
soc/intel/common: Do not trigger crashlog on all resets by default
Crashlog has error records and PMC reset records two parts. When we
send ipc cmd "PMC_IPC_CMD_ID_CRASHLOG_ON_RESET", PMC reset record is
enabled. At each warm/cold/global reset, crashlog would be triggered.
The cause of this crash would be "TRIGGER_ON_ALL_RESETS", it is used to
catch unknown reset reason. At the same time, we would see [Hardware
Error] in the kernel log.
If we default enable TRIGGER_ON_ALL_RESETS, we would have too many false
alarm. Now we disable PMC reset records part by default. And we could
enable it when we need it for the debug purpose.
The generated bert dump is under /var/spool/crash/, we could check this
path to verify this CONFIG disable/enable status.
BUG=b:202737385
TEST=No new bert dump after reset.
Signed-off-by: Curtis Chen <curtis.chen(a)intel.com>
Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/common/Kconfig.common
M src/soc/intel/common/block/crashlog/crashlog.c
M src/soc/intel/tigerlake/Kconfig
4 files changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/59951/4
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