coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/guybrush: Set TPM to to be kernel power managed.
by Karthik Ramasubramanian (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60081 ) Change subject: mb/google/guybrush: Set TPM to to be kernel power managed. ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/60081/comment/416c1673_1e60370a PS4, Line 346: KERNEL_POWER > When PSP_S0I3_RESUME_VERSTAGE is running it needs to be kernel managed to cause the shutdown command […] Ah, I missed it. Thanks for the pointer. -- To view, visit https://review.coreboot.org/c/coreboot/+/60081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I206022cc2a29690186206966c5d45bd55c303248 Gerrit-Change-Number: 60081 Gerrit-PatchSet: 4 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 16:55:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: tests/lib/lzma-test: Fix uninitialized array error
by Jakub Czapiga (Code Review) 14 Dec '21

14 Dec '21

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60112 ) Change subject: tests/lib/lzma-test: Fix uninitialized array error ...................................................................... tests/lib/lzma-test: Fix uninitialized array error Change-Id: I5b10eef3dd82068f97d4d875f3da813a5aca07a7 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reported-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M tests/lib/lzma-test.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/60112/1 diff --git a/tests/lib/lzma-test.c b/tests/lib/lzma-test.c index 3918890..8ae9ced 100644 --- a/tests/lib/lzma-test.c +++ b/tests/lib/lzma-test.c @@ -130,7 +130,7 @@ static void test_ulzman_input_too_small(void **state) { - uint8_t in_buf[32]; + uint8_t in_buf[32] = {0}; uint8_t out_buf[32]; assert_int_equal(0, ulzman(in_buf, LZMA_PROPERTIES_SIZE, out_buf, sizeof(out_buf))); -- To view, visit https://review.coreboot.org/c/coreboot/+/60112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b10eef3dd82068f97d4d875f3da813a5aca07a7 Gerrit-Change-Number: 60112 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/madoo: Generate new SPD ID for new memory parts
by Karthik Ramasubramanian (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Dtrain Hsu, Aseda Aboagye, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59991 ) Change subject: mb/google/dedede/var/madoo: Generate new SPD ID for new memory parts ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b2f447a610a0a857e819ede257ac89cfd817018 Gerrit-Change-Number: 59991 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 14 Dec 2021 16:49:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/fast_spi: Fix ignored build error
by Martin Roth (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Furquan Shaikh, Caveh Jalali, Patrick Rudolph. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49316 ) Change subject: soc/intel/common/fast_spi: Fix ignored build error ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: The code has been rewritten, so this is no longer needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/49316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib579dcba7ffea898345ef0bbc21b0cdcffaedc3e Gerrit-Change-Number: 49316 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 16:37:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/fast_spi: Fix ignored build error
by Martin Roth (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Furquan Shaikh, Caveh Jalali, Patrick Rudolph. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49316 ) Change subject: soc/intel/common/fast_spi: Fix ignored build error ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/fast_spi/Makefile.inc: https://review.coreboot.org/c/coreboot/+/49316/comment/786a34d5_81a48061 PS1, Line 45: $$start > We don't guarantee it, so we should look into alternatives. Stuff like this slips in, though. $((...)) is fine in sh. What shell doesn't it work in? Let's add quotes to the rest in a different commit. This fixes a specific problem, so let's get it merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/49316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib579dcba7ffea898345ef0bbc21b0cdcffaedc3e Gerrit-Change-Number: 49316 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 16:23:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Use relative address for EFS gen2
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56438 ) Change subject: amdfwtool: Use relative address for EFS gen2 ...................................................................... amdfwtool: Use relative address for EFS gen2 The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. The field additional_info in table header can tell if the absolute or relative address is used. Chips like Cezanne can run in both cases, so no problem comes up so far. The related change in psp_verstage has been uploaded. https://review.coreboot.org/c/coreboot/+/58316 The relative mode is the mode 1 of four address modes. The absolute mode is the mode 0. Later we will implement mode 2. Not sure if mode 3 is needed. It needs to be simple to work with psp_verstage change to make SOC Cezanne work quickly. This patch is defacto a subset of https://review.coreboot.org/c/coreboot/+/59308 which implements the framework of address mode and covers mode 0,1,2. Some hardcode value like 29 can be removed in 59308. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56438 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 13 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Kangheui Won: Looks good to me, but someone else must approve diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 98e3189..d8cda92 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -343,11 +343,12 @@ typedef struct _context { char *rom; /* target buffer, size of flash device */ uint32_t rom_size; /* size of flash device */ + uint32_t abs_address; /* produce absolute or relative address */ uint32_t current; /* pointer within flash & proxy buffer */ } context; #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) -#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset)) +#define RUN_OFFSET(ctx, offset) ((ctx).abs_address ? RUN_BASE(ctx) + (offset) : (offset)) #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) @@ -439,6 +440,8 @@ dir->header.cookie = cookie; dir->header.num_entries = count; dir->header.additional_info = (table_size / 0x1000) | (1 << 10); + if (ctx->abs_address == 0) + dir->header.additional_info |= 1 << 29; /* checksum everything that comes after the Checksum field */ dir->header.checksum = fletcher32(&dir->header.num_entries, count * sizeof(psp_directory_entry) @@ -455,6 +458,8 @@ bdir->header.cookie = cookie; bdir->header.num_entries = count; bdir->header.additional_info = (table_size / 0x1000) | (1 << 10); + if (ctx->abs_address == 0) + bdir->header.additional_info |= 1 << 29; /* checksum everything that comes after the Checksum field */ bdir->header.checksum = fletcher32(&bdir->header.num_entries, count * sizeof(bios_directory_entry) @@ -1576,8 +1581,6 @@ romsig_offset = ctx.current = dir_location - rom_base_address; else romsig_offset = ctx.current = AMD_ROMSIG_OFFSET; - printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n", - RUN_CURRENT(ctx)); amd_romsig = BUFF_OFFSET(ctx, romsig_offset); amd_romsig->signature = EMBEDDED_FW_SIGNATURE; @@ -1596,6 +1599,13 @@ fprintf(stderr, "WARNING: No SOC name specified.\n"); } + if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN) + ctx.abs_address = 0; + else + ctx.abs_address = 1; + printf(" AMDFWTOOL Using firmware directory location of %s address: 0x%08x\n", + ctx.abs_address == 1 ? "absolute" : "relative", RUN_CURRENT(ctx)); + integrate_firmwares(&ctx, amd_romsig, amd_fw_table); ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f Gerrit-Change-Number: 56438 Gerrit-PatchSet: 25 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/U-Boot: Fix various build errors
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60028 ) Change subject: payloads/U-Boot: Fix various build errors ...................................................................... payloads/U-Boot: Fix various build errors 1. Fix the inconsistence of the target path of U-Boot payload between Kconfig and Makefile.inc. 2. Perform full clone (to the destined commit) in order to get tags. 3. Move stable commit id of U-Boot payload from Makefile to Kconfig, and make prompt consistent with it. Change-Id: Ic0f11c16274456a452a0422e19fab0c61d8b5d5b Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60028 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- M payloads/external/Makefile.inc M payloads/external/U-Boot/Kconfig M payloads/external/U-Boot/Makefile 3 files changed, 8 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Simon Glass: Looks good to me, approved diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index a185a77..072d8d1 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -197,8 +197,9 @@ # U-Boot -payloads/external/U-Boot/build/u-boot/u-boot.bin u-boot: $(DOTCONFIG) +payloads/external/U-Boot/build/u-boot.bin u-boot: $(DOTCONFIG) $(MAKE) -C payloads/external/U-Boot \ + STABLE_COMMIT_ID=$(CONFIG_UBOOT_STABLE_COMMIT_ID) \ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig index 01dbc95..06b4b73 100644 --- a/payloads/external/U-Boot/Kconfig +++ b/payloads/external/U-Boot/Kconfig @@ -5,12 +5,16 @@ select PAYLOAD_IS_FLAT_BINARY select WANT_LINEAR_FRAMEBUFFER +config UBOOT_STABLE_COMMIT_ID + string + default "v2021.07" + choice prompt "U-Boot version" default UBOOT_STABLE config UBOOT_STABLE - bool "v2019.4" + bool "v2021.07" help Stable U-Boot version diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index daadb3e..07b6f48 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -STABLE_COMMIT_ID=v2021.07 - TAG-$(CONFIG_UBOOT_MASTER)=origin/master TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID) @@ -25,7 +23,7 @@ $(project_dir): echo " Cloning $(project_name) from Git" - git clone --depth 1 $(project_git_repo) $(project_dir) + git clone $(project_git_repo) -b $(TAG-y) $(project_dir) fetch: $(project_dir) ifeq ($(CONFIG_UBOOT_MASTER),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/60028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0f11c16274456a452a0422e19fab0c61d8b5d5b Gerrit-Change-Number: 60028 Gerrit-PatchSet: 11 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: add support for tracker version one
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59989 ) Change subject: soc/mediatek: add support for tracker version one ...................................................................... soc/mediatek: add support for tracker version one There are two versions for tracker system: Version 1 for MT8186, and version 2 for MT8192 and MT8195. Reference document: MT8169_bus_dbg_tracker_cfg_reg.xls from MediaTek internal. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59989 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/tracker_common.h A src/soc/mediatek/common/include/soc/tracker_v1.h A src/soc/mediatek/common/include/soc/tracker_v2.h M src/soc/mediatek/common/tracker.c A src/soc/mediatek/common/tracker_v1.c A src/soc/mediatek/common/tracker_v2.c M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/include/soc/tracker.h M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/tracker.h 10 files changed, 182 insertions(+), 111 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/tracker_common.h b/src/soc/mediatek/common/include/soc/tracker_common.h index a68d329..0269457 100644 --- a/src/soc/mediatek/common/include/soc/tracker_common.h +++ b/src/soc/mediatek/common/include/soc/tracker_common.h @@ -1,25 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_TRACKER_H -#define SOC_MEDIATEK_COMMON_TRACKER_H +#ifndef SOC_MEDIATEK_TRACKER_COMMON_H +#define SOC_MEDIATEK_TRACKER_COMMON_H -#define BUS_DBG_CON 0x000 -#define BUS_DBG_TIMER_CON0 0x004 -#define BUS_DBG_TIMER_CON1 0x008 -#define BUS_TRACE_CON_1 0x900 -#define BUS_TRACE_CON_AO_1 0x9FC -#define BUS_TRACE_CON_2 0xA00 -#define BUS_TRACE_CON_AO_2 0xAFC -#define BUS_TRACE_EN 16 - -#define SYS_TRACK_ENTRY 64 -#define INFRA_ENTRY_NUM 32 -#define PERI_ENTRY_NUM 16 - -#define AR_TRACK_OFFSET 0x0100 -#define AW_TRACK_OFFSET 0x0300 - -#define BUSTRACKER_TIMEOUT 0x300 +#include <stdint.h> #define BUS_DBG_CON_IRQ_AR_STA0 0x00000100 #define BUS_DBG_CON_IRQ_AW_STA0 0x00000200 @@ -28,13 +12,17 @@ #define BUS_DBG_CON_TIMEOUT (BUS_DBG_CON_IRQ_AR_STA0 | BUS_DBG_CON_IRQ_AW_STA0 | \ BUS_DBG_CON_IRQ_AR_STA1 | BUS_DBG_CON_IRQ_AW_STA1) -enum { - TRACKER_SYSTRACKER = 0, - TRACKER_INFRATRACKER, - TRACKER_PERISYSTRACKER, - TRACKER_NUM, +struct tracker { + uintptr_t base_addr; + u32 timeout; + u32 entry; + u32 offset[2]; + const char *str; }; +extern struct tracker tracker_data[]; + +void tracker_setup(void); void bustracker_init(void); #endif diff --git a/src/soc/mediatek/common/include/soc/tracker_v1.h b/src/soc/mediatek/common/include/soc/tracker_v1.h new file mode 100644 index 0000000..e2a4b67 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/tracker_v1.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_TRACKER_V1_H +#define SOC_MEDIATEK_TRACKER_V1_H + +#define SYS_TRACK_ENTRY 8 + +#define AR_TRACK_OFFSET 0x0100 +#define AW_TRACK_OFFSET 0x0200 + +enum { + TRACKER_SYSTRACKER = 0, + TRACKER_NUM, +}; + +#endif diff --git a/src/soc/mediatek/common/include/soc/tracker_v2.h b/src/soc/mediatek/common/include/soc/tracker_v2.h new file mode 100644 index 0000000..e7bf8df --- /dev/null +++ b/src/soc/mediatek/common/include/soc/tracker_v2.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_TRACKER_V2_H +#define SOC_MEDIATEK_TRACKER_V2_H + +#define BUS_DBG_CON 0x000 +#define BUS_DBG_TIMER_CON0 0x004 +#define BUS_DBG_TIMER_CON1 0x008 +#define BUS_TRACE_CON_1 0x900 +#define BUS_TRACE_CON_AO_1 0x9FC +#define BUS_TRACE_CON_2 0xA00 +#define BUS_TRACE_CON_AO_2 0xAFC +#define BUS_TRACE_EN 16 + +#define SYS_TRACK_ENTRY 64 +#define INFRA_ENTRY_NUM 32 +#define PERI_ENTRY_NUM 16 + +#define AR_TRACK_OFFSET 0x0100 +#define AW_TRACK_OFFSET 0x0300 + +#define BUSTRACKER_TIMEOUT 0x300 + +enum { + TRACKER_SYSTRACKER = 0, + TRACKER_INFRATRACKER, + TRACKER_PERISYSTRACKER, + TRACKER_NUM, +}; + +#endif diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 6d4e6b2..f3b2e9b 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -1,81 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdio.h> #include <console/console.h> #include <device/mmio.h> #include <soc/addressmap.h> +#include <soc/tracker.h> #include <soc/tracker_common.h> -static struct tracker { - uintptr_t base_addr; - u32 timeout; - u32 entry; - u32 offset[2]; - const char *str; -} tracker_data[TRACKER_NUM] = { - [TRACKER_SYSTRACKER] = { - .base_addr = DBG_TRACKER_BASE, - .timeout = BUS_DBG_CON_TIMEOUT, - .entry = SYS_TRACK_ENTRY, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, - .str = "systracker", - }, - [TRACKER_INFRATRACKER] = { - .base_addr = INFRA_TRACKER_BASE, - .timeout = BUSTRACKER_TIMEOUT, - .entry = INFRA_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, - .str = "infra_tracker", - }, - [TRACKER_PERISYSTRACKER] = { - .base_addr = PERI_TRACKER_BASE, - .timeout = BUSTRACKER_TIMEOUT, - .entry = PERI_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, - .str = "peri_tracker", - }, -}; - -static void setup_init(void) -{ - u32 val; - /* - * Set infra/peri tracker timeout. - * timeout = clock_in_mhz * 1000 / 16 * timeout_in_ms - * - * timeout: 200ms - * infra tracker clock: 156MHz - * peri tracker clock: 78MHz - */ - val = 156 * 1000 / 16 * 200; - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); - - val = 78 * 1000 / 16 * 200; - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); - - /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); - - /* - * Enable infra/peri tracker. - * bit[0] - BUS_DBG_EN - * bit[1] - TIMEOUT_EN - * bit[2] - SLV_ERR_EN - * bit[13] - HALT_ON_TIMEOUT_EN - * bit[14] - BUS_OT_WEN_CTRL - */ - val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); - -} - static void tracker_dump_data(void) { int i, j, k; @@ -91,19 +21,6 @@ printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); for (k = 0; k < 2; k++) { - /* - * for systracker: - * offset[0] dump from offset 0x100 ~ 0x2F8. - * offset[1] dump from offset 0x300 ~ 0x4FC - * - * for infra tracker: - * offset[0] dump from offset 0x100 ~ 0x1F8 - * offset[1] dump from offset 0x300 ~ 0x3FC - * - * for perisys tracker: - * offset[0] dump from offset 0x100 ~ 0x2F8 - * offset[1] dump from offset 0x300 ~ 0x4FC - */ size = 2 * tra->entry; for (i = 0; i < size; i++) { reg = tra->base_addr + tra->offset[k] + i * 4; @@ -121,5 +38,5 @@ void bustracker_init(void) { tracker_dump_data(); - setup_init(); + tracker_setup(); } diff --git a/src/soc/mediatek/common/tracker_v1.c b/src/soc/mediatek/common/tracker_v1.c new file mode 100644 index 0000000..746951b --- /dev/null +++ b/src/soc/mediatek/common/tracker_v1.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/addressmap.h> +#include <soc/tracker.h> +#include <soc/tracker_common.h> + +/* + * for systracker: + * offset[0] dump from offset 0x100 ~ 0x13C. + * offset[1] dump from offset 0x200 ~ 0x23C. + */ +struct tracker tracker_data[TRACKER_NUM] = { + [TRACKER_SYSTRACKER] = { + .base_addr = DBG_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = SYS_TRACK_ENTRY, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "systracker", + }, +}; diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c new file mode 100644 index 0000000..fecde16 --- /dev/null +++ b/src/soc/mediatek/common/tracker_v2.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/tracker.h> +#include <soc/tracker_common.h> + +/* + * for systracker: + * offset[0] dump from offset 0x100 ~ 0x2F8. + * offset[1] dump from offset 0x300 ~ 0x4FC + * + * for infra tracker: + * offset[0] dump from offset 0x100 ~ 0x1F8 + * offset[1] dump from offset 0x300 ~ 0x3FC + * + * for perisys tracker: + * offset[0] dump from offset 0x100 ~ 0x2F8 + * offset[1] dump from offset 0x300 ~ 0x4FC + */ +struct tracker tracker_data[TRACKER_NUM] = { + [TRACKER_SYSTRACKER] = { + .base_addr = DBG_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = SYS_TRACK_ENTRY, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "systracker", + }, + [TRACKER_INFRATRACKER] = { + .base_addr = INFRA_TRACKER_BASE, + .timeout = BUSTRACKER_TIMEOUT, + .entry = INFRA_ENTRY_NUM, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "infra_tracker", + }, + [TRACKER_PERISYSTRACKER] = { + .base_addr = PERI_TRACKER_BASE, + .timeout = BUSTRACKER_TIMEOUT, + .entry = PERI_ENTRY_NUM, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "peri_tracker", + }, +}; + +void tracker_setup(void) +{ + u32 val; + /* + * Set infra/peri tracker timeout. + * timeout = clock_in_mhz * 1000 / 16 * timeout_in_ms + * + * timeout: 200ms + * infra tracker clock: 156MHz + * peri tracker clock: 78MHz + */ + val = 156 * 1000 / 16 * 200; + write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + + val = 78 * 1000 / 16 * 200; + write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + + /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); + + /* + * Enable infra/peri tracker. + * bit[0] - BUS_DBG_EN + * bit[1] - TIMEOUT_EN + * bit[2] - SLV_ERR_EN + * bit[13] - HALT_ON_TIMEOUT_EN + * bit[14] - BUS_OT_WEN_CTRL + */ + val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); +} diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index b04acb5..aeb50a7 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -10,7 +10,7 @@ bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c -bootblock-y += ../common/tracker.c +bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c diff --git a/src/soc/mediatek/mt8192/include/soc/tracker.h b/src/soc/mediatek/mt8192/include/soc/tracker.h new file mode 100644 index 0000000..0b62811 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/tracker.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_TRACKER_H +#define SOC_MEDIATEK_MT8192_TRACKER_H + +#include <soc/tracker_v2.h> + +#endif diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index a7ada28..8ab78a8 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -7,7 +7,7 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c -bootblock-y += ../common/tracker.c +bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8195/include/soc/tracker.h b/src/soc/mediatek/mt8195/include/soc/tracker.h new file mode 100644 index 0000000..293ce3c --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/tracker.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_TRACKER_H +#define SOC_MEDIATEK_MT8195_TRACKER_H + +#include <soc/tracker_v2.h> + +#endif 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 Gerrit-Change-Number: 59989 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/{cezanne,common}: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60024 ) Change subject: soc/amd/{cezanne,common}: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option ...................................................................... soc/amd/{cezanne,common}: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option Add PSP_S0I3_RESUME_VERSTAGE Kconfig option. When enabled, verstage will be run in PSP during S0i3 resume. Setting softfuse bit 40 enables this in PSP. BUG=b:200578885, b:202397678 BRANCH=None TEST=Verstage runs during s0i3 resume on Nipperkin Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60024 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/psp_verstage/Kconfig 2 files changed, 13 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 58df740..a05da8d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -110,6 +110,10 @@ PSP_SOFTFUSE_BITS += 29 endif +ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) +PSP_SOFTFUSE_BITS += 40 +endif + # Use additional Soft Fuse bits specified in Kconfig PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index 6cac8b7..45a5d22 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -6,10 +6,17 @@ accessing the boot device. Select it on platforms which supports using CCP DMA to access the boot device. +config PSP_S0I3_RESUME_VERSTAGE + bool "S0i3 resume verstage" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default n + help + Select this item to enable running verstage during S0i3 resume. + config PSP_INIT_TPM_ON_S0I3_RESUME bool - depends on TPM2 && VBOOT_STARTS_BEFORE_BOOTBLOCK - default VBOOT_STARTS_BEFORE_BOOTBLOCK + depends on TPM2 && PSP_S0I3_RESUME_VERSTAGE + default PSP_S0I3_RESUME_VERSTAGE help If the TPM is reset while in S0i3, it must be reinitialized during s0i3 resume. This must be performed in PSP verstage since -- To view, visit https://review.coreboot.org/c/coreboot/+/60024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79 Gerrit-Change-Number: 60024 Gerrit-PatchSet: 4 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8
by Angel Pons (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Dmitry Ponamorev, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph, King Sumo. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 ...................................................................... Patch Set 22: (1 comment) File src/mainboard/teleplatforms/D4E4S16P8/romstage.c: https://review.coreboot.org/c/coreboot/+/57194/comment/18a75c71_2a77dfb8 PS20, Line 437: {SOUTH_GROUP0_CTBTRIGINOUT, > Followup, if it ever gets done like that. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 22 Gerrit-Owner: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 15:37:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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