coreboot-gerrit December 2021

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Change in coreboot[master]: soc/amd/common/block/spi/fch_spi_ctrl: handle failure in execute_command
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

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Change in coreboot[master]: soc/amd/common/block/spi/fch_spi_ctrl: rework dump_state
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60118 ) Change subject: soc/amd/common/block/spi/fch_spi_ctrl: rework dump_state ...................................................................... soc/amd/common/block/spi/fch_spi_ctrl: rework dump_state Introduce and use enum spi_dump_state_phase to indicate from which phase of the SPI transfer dump_state gets called to print the relevant debug information for that phase. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2f54d4a7eb2f3b9756b77a01533f7c99e8597bfa --- M src/soc/amd/common/block/spi/fch_spi_ctrl.c 1 file changed, 25 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/60118/1 diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index d95b642..aad8de7 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -30,7 +30,12 @@ #define SPI_FIFO_RD_PTR_SHIFT 16 #define SPI_FIFO_RD_PTR_MASK 0x7f -static void dump_state(const char *str, u8 phase) +enum spi_dump_state_phase { + SPI_DUMP_STATE_BEFORE_CMD, + SPI_DUMP_STATE_AFTER_CMD, +}; + +static void dump_state(enum spi_dump_state_phase phase) { u8 dump_size; u32 addr; @@ -38,19 +43,33 @@ if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) return; - printk(BIOS_DEBUG, "SPI: %s\n", str); + switch (phase) { + case SPI_DUMP_STATE_BEFORE_CMD: + printk(BIOS_DEBUG, "SPI: Before execute\n"); + break; + case SPI_DUMP_STATE_AFTER_CMD: + printk(BIOS_DEBUG, "SPI: Transaction finished\n"); + break; + default: /* We shouldn't reach this */ + return; + } + printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); addr = spi_get_bar() + SPI_FIFO; - if (phase == 0) { + + switch (phase) { + case SPI_DUMP_STATE_BEFORE_CMD: dump_size = spi_read8(SPI_TX_BYTE_COUNT); printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); - } else { + break; + case SPI_DUMP_STATE_AFTER_CMD: dump_size = spi_read8(SPI_RX_BYTE_COUNT); printk(BIOS_DEBUG, "RxByteCount: %x\n", dump_size); addr += spi_read8(SPI_TX_BYTE_COUNT); + break; } if (dump_size > 0) @@ -74,7 +93,7 @@ static int execute_command(void) { - dump_state("Before execute", 0); + dump_state(SPI_DUMP_STATE_BEFORE_CMD); spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); @@ -82,7 +101,7 @@ printk(BIOS_ERR, "FCH_SC Error: Timeout executing command\n"); - dump_state("Transaction finished", 1); + dump_state(SPI_DUMP_STATE_AFTER_CMD); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/60118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f54d4a7eb2f3b9756b77a01533f7c99e8597bfa Gerrit-Change-Number: 60118 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/include/spi: add Cezanne-specific comment
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

1 0

Change in coreboot[master]: soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60116 ) Change subject: soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define ...................................................................... soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of the SPI controller's MMIO region for Stoneyridge and Picasso. Both SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH isn't changed. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628 --- M src/soc/amd/common/block/include/amdblocks/spi.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60116/1 diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 5c3bd0e..4efed68 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -71,8 +71,8 @@ #define SPI_RD4DW_EN_HOST BIT(15) #define SPI_FIFO 0x80 -#define SPI_FIFO_LAST_BYTE 0xc7 -#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO) +#define SPI_FIFO_LAST_BYTE 0xc6 +#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) struct spi_config { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/60116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628 Gerrit-Change-Number: 60116 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp_n: Add initial code for adl-n variant board
by Angel Pons (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Reka Norman, Krishna P Bhat D, Usha P, Kangheui Won. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59915 ) Change subject: mb/intel/adlrvp_n: Add initial code for adl-n variant board ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Gerrit-Change-Number: 59915 Gerrit-PatchSet: 7 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 21:55:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cbfstool: Clean up remnants of locate action
by Julius Werner (Code Review) 14 Dec '21

14 Dec '21

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60085 ) Change subject: cbfstool: Clean up remnants of locate action ...................................................................... cbfstool: Clean up remnants of locate action `cbfstool locate` and the associated -T switch were removed a looong time ago (2015 in CB:11671). However, getopt and the help text weren't cleaned up correctly. Fix that. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ib098278d68df65d348528fbfd2496b5737ca6246 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60085 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M util/cbfstool/cbfstool.c 1 file changed, 1 insertion(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index a84601e..608cd32 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1771,7 +1771,6 @@ {"pow2page", no_argument, 0, 'Q' }, {"ucode-region", required_argument, 0, 'q' }, {"size", required_argument, 0, 's' }, - {"top-aligned", required_argument, 0, 'T' }, {"type", required_argument, 0, 't' }, {"verbose", no_argument, 0, 'v' }, {"with-readonly", no_argument, 0, 'w' }, @@ -1927,9 +1926,6 @@ "Create a legacy ROM file with CBFS master header*\n" " create -M flashmap [-r list,of,regions,containing,cbfses] " "Create a new-style partitioned firmware image\n" - " locate [-r image,regions] -f FILE -n NAME [-P page-size] \\\n" - " [-a align] [-T] " - "Find a place for a file of that size\n" " layout [-w] " "List mutable (or, with -w, readable) image regions\n" " print [-r image,regions] [-k] " @@ -1964,8 +1960,7 @@ " specifying the location of this FMAP itself and a '%s'\n" " section describing the primary CBFS. It should also be noted\n" " that, when working with such images, the -F and -r switches\n" - " default to '%s' for convenience, and both the -b switch to\n" - " CBFS operations and the output of the locate action become\n" + " default to '%s' for convenience, and the -b switch becomes\n" " relative to the selected CBFS region's lowest address.\n" " The one exception to this rule is the top-aligned address,\n" " which is always relative to the end of the entire image\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/60085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib098278d68df65d348528fbfd2496b5737ca6246 Gerrit-Change-Number: 60085 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cbfstool: Use converted buffer size for do_cbfs_locate()
by Julius Werner (Code Review) 14 Dec '21

14 Dec '21

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60084 ) Change subject: cbfstool: Use converted buffer size for do_cbfs_locate() ...................................................................... cbfstool: Use converted buffer size for do_cbfs_locate() The whole point of moving do_cbfs_locate() later (CB:59877) was that it could use the file size that is actually going to be inserted into CBFS, rather than the on-disk file size. Unfortunately, after all that work I forgot to actually make it do that. This patch fixes that. Since there is no more use case for do_cbfs_locate() having to figure out the file size on its own, and that generally seems to be a bad idea (as the original issue shows), also remove that part of it completely and make the data_size parameter mandatory. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I1af35e8e388f78aae3593c029afcfb4e510d2b8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60084 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M util/cbfstool/cbfstool.c 1 file changed, 6 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 77460d1..a84601e 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -511,11 +511,6 @@ { uint32_t metadata_size = 0; - if (!param.filename) { - ERROR("You need to specify -f/--filename.\n"); - return 1; - } - if (!param.name) { ERROR("You need to specify -n/--name.\n"); return 1; @@ -530,17 +525,10 @@ WARN("'%s' already in CBFS.\n", param.name); if (!data_size) { - struct buffer buffer; - if (buffer_from_file(&buffer, param.filename) != 0) { - ERROR("Cannot load %s.\n", param.filename); - return 1; - } - data_size = buffer.size; - buffer_delete(&buffer); + ERROR("File '%s' is empty?\n", param.name); + return 1; } - DEBUG("File size is %zd (0x%zx)\n", data_size, data_size); - /* Compute required page size */ if (param.force_pow2_pagesize) { param.pagesize = 1; @@ -571,8 +559,8 @@ param.alignment, metadata_size); if (address < 0) { - ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", - param.name, param.pagesize, param.alignment); + ERROR("'%s'(%u + %zu) can't fit in CBFS for page-size %#x, align %#x.\n", + param.name, metadata_size, data_size, param.pagesize, param.alignment); return 1; } @@ -917,7 +905,7 @@ /* This needs to run after convert() to take compression into account. */ if (!offset && param.alignment) - if (do_cbfs_locate(&offset, 0)) + if (do_cbfs_locate(&offset, buffer_size(&buffer))) goto error; /* This needs to run after convert() to hash the actual final file data. */ @@ -1076,7 +1064,7 @@ if (param.stage_xip) { if (!param.baseaddress_assigned) { param.alignment = 4*1024; - if (do_cbfs_locate(offset, 0)) + if (do_cbfs_locate(offset, buffer_size(buffer))) return -1; } assert(!IS_HOST_SPACE_ADDRESS(*offset)); -- To view, visit https://review.coreboot.org/c/coreboot/+/60084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1af35e8e388f78aae3593c029afcfb4e510d2b8f Gerrit-Change-Number: 60084 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/anahera{4es}: Add Chrome OS privacy screen _HID
by Tim Wawrzynczak (Code Review) 14 Dec '21

14 Dec '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60115 ) Change subject: mb/google/brya/var/anahera{4es}: Add Chrome OS privacy screen _HID ...................................................................... mb/google/brya/var/anahera{4es}: Add Chrome OS privacy screen _HID Similar to commit 0167f5adb (mb/google/redrix: Add _HID for privacy screen device), add the same _HID to the privacy screen device. Change-Id: I58ad538dfaf602e3f4afb98d1a25d52753a15d93 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/60115/1 diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index dc563a4..6d268c7 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -72,6 +72,8 @@ chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index dc563a4..6d268c7 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -72,6 +72,8 @@ chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/60115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58ad538dfaf602e3f4afb98d1a25d52753a15d93 Gerrit-Change-Number: 60115 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/variants/brask: disabled autonomous GPIO power management
by Tim Wawrzynczak (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60100 ) Change subject: mb/google/brya/variants/brask: disabled autonomous GPIO power management ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60100/comment/2cd319e8_4fa44c14 PS1, Line 7: disabled `Disable` -- To view, visit https://review.coreboot.org/c/coreboot/+/60100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5 Gerrit-Change-Number: 60100 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 21:01:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update overridetree for SSD setting
by Tim Wawrzynczak (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Kevin Chiu, Robert Chen, Wisley Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60099 ) Change subject: mb/google/brya/var/vell: update overridetree for SSD setting ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Can this also be squashed into 59304? -- To view, visit https://review.coreboot.org/c/coreboot/+/60099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37 Gerrit-Change-Number: 60099 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 21:00:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021