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Change subject: amdfwtool: Upgrade "relative address" to four address modes
......................................................................
Patch Set 11:
(2 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/59308/comment/8984c07b_f5dc561b
PS10, Line 353: 0
> it would probably be good to add some defines for these values and use those here and also in the re […]
Done
https://review.coreboot.org/c/coreboot/+/59308/comment/3505a200_376bac6a
PS10, Line 371: mode, table
> i would swap the order of table and mode; having the table first would be more what i'd expect there
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Kangheui Won, Paul Menzel, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#11).
Change subject: amdfwtool: Upgrade "relative address" to four address modes
......................................................................
amdfwtool: Upgrade "relative address" to four address modes
Address Mode 0: Physical Address, bit 63~56: 0x00
Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40
Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80
Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0
It is the expanding mode for simple relative address mode, for which
address_mode equals 1.
Only mode 2 is added. We need to record current table base address and
calculate the offset. The ctx.current_table is zero outside the
table. When it goes into the function to integrate the table, it
should backup the old value and get current table base. Before it goes
out the function, it should restore the value.
If the table address mode is 2, the address in each entry should be
also add address mode information. If not, the address mode in entry
is meanless.
The old mode 0,1 should be back compatible.
Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 98 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59308/11
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Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60099 )
Change subject: mb/google/brya/var/vell: update overridetree for SSD setting
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Can this also be squashed into 59304?
Hi Tim,
since the CLKREQ/CLKSRC was revised per Intel's suggestion and it differs to fit setting, will it be good to separate it for a record? thanks.
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Change subject: mb/google/guybrush/var/dewatt: Add audio codec
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
Hi Rob/Karthik, audio can work with the CL, please help to review the CL. Thanks.
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Change subject: mb/google/brya/var/primus: Update thermal table for primus
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/primus/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/60101/comment/b82a39d8_37013140
PS4, Line 109: 89
> If you insert the extra TSR at position 0, then keep in mind that, for example, this 89 will apply t […]
Hi Tim,
Yes,this 89 is for SSD. thanks~😊
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Change subject: mb/google/brya/variants/brask: Disable autonomous GPIO power management
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60100/comment/a505cc26_d03206aa
PS1, Line 7: disabled
> `Disable`
Done
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/variants/brask: Disable autonomous GPIO power management
......................................................................
mb/google/brya/variants/brask: Disable autonomous GPIO power management
We found that the `Cr50 i2c TPM IRQ timeout!` error when the device
executed the reboot test even though we have updated the cr50
firmware to the 0.6.70. Besides, we also need to avoid the factory
power on issue when using the 0.3.22 cr50 firmware. So, we submitted
this patch to disable the gpio power management.
BUG=b:210540890
TEST=reboot 100 cycles without the error message.
Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5
Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org>
---
M src/mainboard/google/brya/variants/brask/overridetree.cb
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/60100/2
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Change subject: mb/google/guybrush/var/dewatt: Add audio codec
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60021/comment/d9754441_76a70707
PS1, Line 9: Add ALC5682-VD and ALC1019 for dewatt.
> Where? I only see RT5682?
https://partnerissuetracker.corp.google.com/issues/208172493#comment4 , please refer the comment
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Hello Tim Wawrzynczak, Patrick Rudolph,
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Change subject: soc/intel/alderlake: do not lock GPP_B16/ GPP_B17
......................................................................
soc/intel/alderlake: do not lock GPP_B16/ GPP_B17
Do not lock GPP_B16/ GPP_B17 because we set it as NF2. This will let i2c device lost function after warm reboot.
BUG=b:210701402
BRANCH=none
TEST=after warm reboot, the touchpad still work.
Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com>
Change-Id: I106ddc96c3185656d3f1fbcd45f198d2d46f3f4d
---
M src/soc/intel/alderlake/gpio.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/60126/2
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