coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/alderlake: do not lock GPP_B16/ GPP_B17
by Scott Chao (Code Review) 15 Dec '21

15 Dec '21

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60126 ) Change subject: soc/intel/alderlake: do not lock GPP_B16/ GPP_B17 ...................................................................... soc/intel/alderlake: do not lock GPP_B16/ GPP_B17 Do not lock GPP_B16/ GPP_B17 because we set it as NF2. This will let i2c device lost function after warm reboot. Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I106ddc96c3185656d3f1fbcd45f198d2d46f3f4d --- M src/soc/intel/alderlake/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/60126/1 diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index aa05136e..40e23d6 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -259,8 +259,6 @@ { GPP_B8, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SCL NF1 */ { GPP_B14, GPIO_LOCK_CONFIG }, /* ISH_GP6 NF5 */ { GPP_B15, GPIO_LOCK_CONFIG }, /* ISH_GP7 NF5 */ - { GPP_B16, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SDA NF4 */ - { GPP_B17, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SCL NF4 */ { GPP_D0, GPIO_LOCK_CONFIG }, /* ISH_GP0 NF1 */ { GPP_D1, GPIO_LOCK_CONFIG }, /* ISH_GP1 NF1 */ { GPP_D2, GPIO_LOCK_CONFIG }, /* ISH_GP2 NF1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I106ddc96c3185656d3f1fbcd45f198d2d46f3f4d Gerrit-Change-Number: 60126 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Upgrade "relative address" to four address modes
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59308 ) Change subject: amdfwtool: Upgrade "relative address" to four address modes ...................................................................... Patch Set 10: (3 comments) Patchset: PS10: the patch seems to need to be rebased; at least the submit button is grayed out for me File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/59308/comment/ab5efc9d_d69a56fe PS10, Line 353: 0 it would probably be good to add some defines for these values and use those here and also in the rest of the code https://review.coreboot.org/c/coreboot/+/59308/comment/90a572a9_613b046d PS10, Line 371: mode, table i would swap the order of table and mode; having the table first would be more what i'd expect there -- To view, visit https://review.coreboot.org/c/coreboot/+/59308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Gerrit-Change-Number: 59308 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Tue, 14 Dec 2021 23:46:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c
by Marshall Dawson (Code Review) 15 Dec '21

15 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60124 ) Change subject: soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b Gerrit-Change-Number: 60124 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 14 Dec 2021 23:38:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/amd/cezanne/fch: disable 48MHz output in S0i3
by Felix Held (Code Review) 15 Dec '21

15 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60125 ) Change subject: [UNTESTED] soc/amd/cezanne/fch: disable 48MHz output in S0i3 ...................................................................... [UNTESTED] soc/amd/cezanne/fch: disable 48MHz output in S0i3 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If445f5825dc7b795c95d73c061156cc485421ada --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/include/soc/southbridge.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/60125/1 diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 8cd1212..2c57f08 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -78,6 +78,8 @@ uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); /* Enable BP_X48M0 Clock Output */ ctrl |= BP_X48M0_OUTPUT_EN; + /* Disable clock output in S0i3 */ + ctrl |= BP_X48M0_S0I3_DIS; misc_write32(MISC_CLK_CNTL0, ctrl); } diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 3bba559..4f372ad 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -110,6 +110,7 @@ #define USB_PHY_CMCLK_S0I3_DIS BIT(9) #define USB_PHY_CMCLK_S5_DIS BIT(10) #define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ +#define BP_X48M0_S0I3_DIS BIT(4) #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define MISC_I2C0_PAD_CTRL 0xd8 #define MISC_I2C1_PAD_CTRL 0xdc -- To view, visit https://review.coreboot.org/c/coreboot/+/60125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Gerrit-Change-Number: 60125 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: rules.h, thread.h, lib/cbfs: Add ENV_STAGE_SUPPORTS_COOP
by Julius Werner (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Raul Rangel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59550 ) Change subject: rules.h, thread.h, lib/cbfs: Add ENV_STAGE_SUPPORTS_COOP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1197406d1d36391998b08e3076146bb2fff59d00 Gerrit-Change-Number: 59550 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 22:46:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60124 ) Change subject: soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c ...................................................................... soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c The MBOX_BIOS_CMD_DRAM_INFO PSP mailbox command is only available on the first generation of PSP mailbox interface and not on the second generation. The second generation of the PSP mailbox interface was introduced with the AMD family 17h SoCs on which the DRAM is already initialized before the x86 cores are released from reset. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen1.c 4 files changed, 27 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/60124/1 diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index e749d75..c9986ca 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -51,6 +51,8 @@ #define PSPSTS_INVALID_NAME 8 #define PSPSTS_INVALID_BLOB 9 +/* PSP gen1-only. SoCs with PSP gen2 already have the DRAM initialized when + the x86 cores are released from reset. */ int psp_notify_dram(void); int psp_notify_smm(void); diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index b955459..66f7d59 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -56,29 +56,6 @@ } /* - * Notify the PSP that DRAM is present. Upon receiving this command, the PSP - * will load its OS into fenced DRAM that is not accessible to the x86 cores. - */ -int psp_notify_dram(void) -{ - int cmd_status; - struct mbox_default_buffer buffer = { - .header = { - .size = sizeof(buffer) - } - }; - - printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... "); - - cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); - - /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, &buffer.header); - - return cmd_status; -} - -/* * Notify the PSP that the system is completing the boot process. Upon * receiving this command, the PSP will only honor commands where the buffer * is in SMM space. diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 4d3aca5..5baa064 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -8,7 +8,6 @@ #include <amdblocks/psp.h> /* x86 to PSP commands */ -#define MBOX_BIOS_CMD_DRAM_INFO 0x01 #define MBOX_BIOS_CMD_SMM_INFO 0x02 #define MBOX_BIOS_CMD_SX_INFO 0x03 #define MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX 0x07 @@ -19,7 +18,8 @@ #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 #define MBOX_BIOS_CMD_NOP 0x09 #define MBOX_BIOS_CMD_ABORT 0xfe -/* x86 to PSP commands, v1 */ +/* x86 to PSP commands, v1-only */ +#define MBOX_BIOS_CMD_DRAM_INFO 0x01 #define MBOX_BIOS_CMD_SMU_FW 0x19 #define MBOX_BIOS_CMD_SMU_FW2 0x1a diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 55070f2..37257ba 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -170,3 +170,26 @@ cbfs_unmap(blob); return cmd_status; } + +/* + * Notify the PSP that DRAM is present. Upon receiving this command, the PSP + * will load its OS into fenced DRAM that is not accessible to the x86 cores. + */ +int psp_notify_dram(void) +{ + int cmd_status; + struct mbox_default_buffer buffer = { + .header = { + .size = sizeof(buffer) + } + }; + + printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... "); + + cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, &buffer.header); + + return cmd_status; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b Gerrit-Change-Number: 60124 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/starlabs/labtop: Tidy up GPIOs
by Sean Rhodes (Code Review) 14 Dec '21

14 Dec '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60123 ) Change subject: mb/starlabs/labtop: Tidy up GPIOs ...................................................................... mb/starlabs/labtop: Tidy up GPIOs Add label to GPIO and categorise per device Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a --- M src/mainboard/starlabs/labtop/variants/tgl/gpio.c 1 file changed, 395 insertions(+), 196 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/60123/1 diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c index a541c07..b48bc28 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c @@ -9,8 +9,11 @@ /* Early pad configuration in romstage. */ const struct pad_config early_gpio_table[] = { - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* + * UART 2: Debug + */ + /* RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; const struct pad_config *variant_early_gpio_table(size_t *num) @@ -21,200 +24,396 @@ /* Pad configuration in ramstage.c */ const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), - PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), - PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), - PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), - PAD_CFG_GPO(GPD7, 0, PWROK), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), - PAD_CFG_NF(GPD9, NONE, PWROK, NF1), - PAD_CFG_NF(GPD10, NONE, PWROK, NF1), - PAD_CFG_GPO(GPD11, 0, PWROK), - PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_NC(GPP_A7, NONE), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), - PAD_NC(GPP_A10, NONE), - PAD_CFG_GPO(GPP_A11, 1, PLTRST), - PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), - PAD_NC(GPP_A13, NONE), - PAD_CFG_GPO(GPP_A14, 0, PLTRST), - PAD_NC(GPP_A15, NONE), - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - PAD_NC(GPP_A17, NONE), - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - PAD_NC(GPP_A19, NONE), - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), - PAD_NC(GPP_A22, NONE), - PAD_CFG_GPO(GPP_A23, 0, PLTRST), - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - PAD_NC(GPP_B2, NONE), - PAD_NC(GPP_B3, NONE), - PAD_NC(GPP_B4, NONE), - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_NC(GPP_B8, NONE), - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_B14, 1, PLTRST), - PAD_NC(GPP_B15, NONE), - PAD_NC(GPP_B16, NONE), - PAD_CFG_GPO(GPP_B17, 0, PWROK), - PAD_CFG_GPO(GPP_B18, 0, DEEP), - PAD_NC(GPP_B19, NONE), - PAD_NC(GPP_B20, NONE), - PAD_NC(GPP_B21, NONE), - PAD_CFG_GPO(GPP_B22, 0, DEEP), - PAD_CFG_GPO(GPP_B23, 0, DEEP), - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_C2, 0, DEEP), - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_C5, 0, DEEP), - PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), - PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), - PAD_NC(GPP_C9, NONE), - PAD_CFG_GPO(GPP_C10, 0, PWROK), - PAD_CFG_GPO(GPP_C11, 0, PWROK), - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_C13, 1, PLTRST), - PAD_NC(GPP_C14, NONE), - PAD_NC(GPP_C15, NONE), - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - PAD_NC(GPP_C22, NONE), - PAD_NC(GPP_C23, NONE), - PAD_NC(GPP_D0, NONE), - PAD_NC(GPP_D1, NONE), - PAD_CFG_GPI(GPP_D2, NONE, DEEP), - PAD_CFG_GPI(GPP_D3, NONE, DEEP), - PAD_NC(GPP_D4, NONE), - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), - PAD_NC(GPP_D9, NATIVE), - PAD_NC(GPP_D10, NATIVE), - PAD_NC(GPP_D11, NATIVE), - PAD_NC(GPP_D12, NATIVE), - PAD_NC(GPP_D13, NONE), - PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_CFG_GPO(GPP_D16, 1, PLTRST), - PAD_CFG_GPI(GPP_D17, NONE, DEEP), - PAD_CFG_GPI(GPP_D18, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP), - PAD_NC(GPP_E0, NONE), - PAD_NC(GPP_E1, NONE), - PAD_NC(GPP_E2, NONE), - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), - PAD_NC(GPP_E4, NONE), - PAD_NC(GPP_E5, NONE), - PAD_NC(GPP_E6, NONE), - PAD_NC(GPP_E7, NONE), - PAD_NC(GPP_E8, NONE), - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - PAD_NC(GPP_E10, NONE), - PAD_NC(GPP_E11, NONE), - PAD_NC(GPP_E12, NONE), - PAD_NC(GPP_E13, NONE), - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2), - PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), - PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NATIVE), - PAD_NC(GPP_E19, NATIVE), - PAD_NC(GPP_E20, NATIVE), - PAD_NC(GPP_E21, NATIVE), - PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF2), - PAD_CFG_GPO(GPP_E23, 0, DEEP), - PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), - PAD_NC(GPP_F6, NONE), - PAD_CFG_GPO(GPP_F7, 1, PLTRST), - PAD_NC(GPP_F8, NONE), - PAD_CFG_GPO(GPP_F9, 1, PLTRST), - PAD_CFG_GPO(GPP_F10, 0, DEEP), - PAD_NC(GPP_F11, NONE), - PAD_NC(GPP_F12, NONE), - PAD_NC(GPP_F13, NONE), - PAD_NC(GPP_F14, NONE), - PAD_NC(GPP_F15, NONE), - PAD_NC(GPP_F16, NONE), - PAD_NC(GPP_F17, NONE), - PAD_NC(GPP_F18, NONE), - PAD_NC(GPP_F19, NONE), - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - PAD_NC(GPP_F22, NONE), - PAD_NC(GPP_F23, NONE), - PAD_CFG_GPO(GPP_H0, 0, DEEP), - PAD_CFG_GPO(GPP_H1, 0, DEEP), - PAD_CFG_GPO(GPP_H2, 0, DEEP), - PAD_NC(GPP_H3, NONE), - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), - PAD_NC(GPP_H10, NONE), - PAD_NC(GPP_H11, NONE), - PAD_NC(GPP_H12, NONE), - PAD_NC(GPP_H13, NONE), - PAD_CFG_GPO(GPP_H14, 1, PLTRST), - PAD_NC(GPP_H15, NONE), - PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - PAD_NC(GPP_H19, NONE), - PAD_NC(GPP_H20, NONE), - PAD_NC(GPP_H21, NONE), - PAD_NC(GPP_H22, NONE), - PAD_CFG_GPO(GPP_H23, 0, DEEP), - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_R5, 0, PLTRST), - PAD_CFG_GPO(GPP_R6, 1, PLTRST), - PAD_NC(GPP_R7, NONE), - PAD_NC(GPP_S0, NONE), - PAD_NC(GPP_S1, NONE), - PAD_NC(GPP_S2, NONE), - PAD_NC(GPP_S3, NONE), - PAD_NC(GPP_S4, NONE), - PAD_NC(GPP_S5, NONE), - PAD_NC(GPP_S6, NONE), - PAD_NC(GPP_S7, NONE), - PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), - PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), - PAD_NC(GPP_U4, NONE), - PAD_NC(GPP_U5, NONE), + /* BATLOW */ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + /* ACPRESENT */ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + /* LAN WAKE */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + /* PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + /* S3 */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + /* S4 */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + /* A */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + /* GPD 7 */ PAD_CFG_GPO(GPD7, 0, PWROK), + /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + /* WLAN */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + /* S5 */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + /* LANPHYPC */ PAD_CFG_GPO(GPD11, 0, PWROK), + + /* + * ESPI + */ + /* IO 0 */ PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* IO 1 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* IO 2 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* IO 3 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* CS */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* CLK */ PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + /* RESET */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* + * Power Managent Controller + */ + /* ALERT */ PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), + + /* SLP S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* PLTRST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* + * GSPI 0: ? + */ + /* CS0 */ PAD_NC(GPP_B15, NONE), + /* CLK */ PAD_NC(GPP_B16, NONE), + /* MISO */ PAD_CFG_GPO(GPP_B17, 0, PWROK), + /* MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP), + + /* + * GSPI 1: ? + */ + /* CS0 */ PAD_NC(GPP_B19, NONE), + /* CLK */ PAD_NC(GPP_B20, NONE), + /* MISO */ PAD_NC(GPP_B21, NONE), + /* MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP), + + /* + * SMBus + */ + /* CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* ALERT */ PAD_CFG_GPO(GPP_C2, 0, DEEP), + + /* + * SML 0 + */ + /* CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* ALERT */ PAD_CFG_GPO(GPP_C5, 0, DEEP), + + /* + * SML 1 + */ + /* CLK */ PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), + /* DATA */ PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), + /* ALERT */ PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* + * VR + */ + /* ALERT */ PAD_NC(GPP_B2, NONE), + + /* + * CNV + */ + /* BRI DT */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* BRI RSP */ PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* RGI DT */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* RGI FSP */ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* RF RESET */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* MODEL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* PA BLANK */ PAD_NC(GPP_F6, NONE), + + /* + * UART 0: Trackpad + */ + /* RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* TXD */ PAD_NC(GPP_C9, NONE), + /* RTS */ PAD_CFG_GPO(GPP_C10, 0, PWROK), + /* CTS */ PAD_CFG_GPO(GPP_C11, 0, PWROK), + + /* + * UART 1: Integrated Sensor Hub + */ + /* RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* TXD */ PAD_CFG_GPO(GPP_C13, 1, PLTRST), + /* RTS */ PAD_NC(GPP_C14, NONE), + /* CTS */ PAD_NC(GPP_C15, NONE), + + /* + * I2C 0 + */ + /* SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + + /* + * I2C 1 + */ + /* SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* + * UART 2: Debug + */ + /* RTS */ PAD_NC(GPP_C22, NONE), + /* CTS */ PAD_NC(GPP_C23, NONE), + + /* + * Integrated Sensor Hub + */ + /* GP 0 */ PAD_NC(GPP_D0, NONE), + /* GP 1 */ PAD_NC(GPP_D1, NONE), + /* GP 2 */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* GP 3 */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* GP 4 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), + /* GP 5 */ PAD_CFG_GPI(GPP_D18, NONE, DEEP), + /* GP 6 */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2), + /* GP 7 */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), + + /* CS */ PAD_NC(GPP_D9, NATIVE), + /* CLK */ PAD_NC(GPP_D10, NATIVE), + /* MISO */ PAD_NC(GPP_D11, NATIVE), + /* MOSI */ PAD_NC(GPP_D12, NATIVE), + + /* RXD */ PAD_NC(GPP_D13, NONE), + /* TXD */ PAD_NC(GPP_D14, NONE), + /* RTS */ PAD_NC(GPP_D15, NONE), + /* CTS */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), + + /* + * ISH I2C 0 + */ + /* SDA */ PAD_NC(GPP_B5, NONE), + /* SCL */ PAD_NC(GPP_B6, NONE), + + /* + * ISH I2C 1 + */ + /* SDA */ PAD_NC(GPP_B7, NONE), + /* SCL */ PAD_NC(GPP_B8, NONE), + + /* + * ISH I2C 2 + */ + /* SDA */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + + /* + * Clock Request + */ + /* REQ 0 */ PAD_NC(GPP_D5, NONE), + /* REQ 1 */ PAD_NC(GPP_D6, NONE), + /* REQ 2 */ PAD_NC(GPP_D7, NONE), + /* REQ 3 */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* REQ 4 */ PAD_NC(GPP_H10, NONE), + /* REQ 5 */ PAD_NC(GPP_H11, NONE), + /* REQ 6 */ PAD_NC(GPP_F19, NONE), + + /* + * SATA + */ + /* GP 0 */ PAD_NC(GPP_E0, NONE), + /* LED */ PAD_NC(GPP_E8, NONE), + + /* + * Dev + */ + /* SLP 0 */ PAD_NC(GPP_E4, NONE), + /* SLP 1 */ PAD_NC(GPP_E5, NONE), + + /* + * THC 0 + */ + /* RST */ PAD_NC(GPP_E6, NONE), + /* INT */ PAD_NC(GPP_E17, NONE), + /* SPI 1 CS */ PAD_NC(GPP_E10, NONE), + /* SPI 1 CLK */ PAD_NC(GPP_E11, NONE), + /* SPI 1 IO0 */ PAD_NC(GPP_E13, NONE), + /* SPI 1 IO1 */ PAD_NC(GPP_E12, NONE), + /* SPI 1 IO2 */ PAD_NC(GPP_E1, NONE), + /* SPI 1 IO3 */ PAD_NC(GPP_E2, NONE), + + /* + * THC 1 + */ + /* RST */ PAD_NC(GPP_F17, NONE), + /* INT */ PAD_NC(GPP_F18, NONE), + /* SPI 2 CS */ PAD_NC(GPP_F16, NONE), + /* SPI 2 CLK */ PAD_NC(GPP_F11, NONE), + /* SPI 2 IO0 */ PAD_NC(GPP_F12, NONE), + /* SPI 2 IO1 */ PAD_NC(GPP_F13, NONE), + /* SPI 2 IO2 */ PAD_NC(GPP_F14, NONE), + /* SPI 2 IO3 */ PAD_NC(GPP_F15, NONE), + + /* + * USB + */ + /* OC 0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + + /* OC 2 */ PAD_NC(GPP_A15, NONE), + /* OC 3 */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* + * DISP + */ + /* MISCC */ PAD_NC(GPP_A17, NONE), + + /* + * DDSP + */ + /* HPDA */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* DPDB */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* HPD 1 */ PAD_NC(GPP_A19, NONE), + /* HPD 2 */ PAD_NC(GPP_A20, NONE), + + /* F7 */ PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* F9 */ PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* F10 */ PAD_CFG_GPO(GPP_F10, 0, DEEP), + + /* + * External Power + */ + /* GATE 1 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* GATE 2 */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + + /* VNN CTRL */ PAD_NC(GPP_F22, NONE), + /* V1P05 */ PAD_NC(GPP_F23, NONE), + + /* H0 */ PAD_CFG_GPO(GPP_H0, 0, DEEP), + /* H1 */ PAD_CFG_GPO(GPP_H1, 0, DEEP), + /* H2 */ PAD_CFG_GPO(GPP_H2, 0, DEEP), + + /* + * I2C 2 + */ + /* SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* + * I2C 3 + */ + /* SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* + * I2C 4 + */ + /* SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + + /* + * M2 SKT 2 + */ + /* CFG 0 */ PAD_NC(GPP_H12, NONE), + /* CFG 1 */ PAD_NC(GPP_H13, NONE), + /* CFG 2 */ PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* CFG 3 */ PAD_NC(GPP_H15, NONE), + + /* + * DDPA + */ + /* CTRL CLK */ PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF2), + /* CTRL DATA */ PAD_CFG_GPO(GPP_E23, 0, DEEP), + + /* + * DDPB + */ + /* CTRL CLK */ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* CTRL DATA */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* + * DDPC + */ + /* CTRL CLK */ PAD_NC(GPP_A21, NONE), + /* CTRL DATA */ PAD_NC(GPP_A22, NONE), + + /* DDP1 */ + /* CTRL CLK */ PAD_NC(GPP_E18, NATIVE), + /* CTRL DATA */ PAD_NC(GPP_E19, NATIVE), + + /* DDP2 */ + /* CTRL CLK */ PAD_NC(GPP_E20, NATIVE), + /* CTRL DATA */ PAD_NC(GPP_E21, NATIVE), + + /* + * CPU + */ + /* C10 GATE */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), + /* GP1 */ PAD_NC(GPP_E7, NONE), + /* GP2 */ PAD_NC(GPP_B3, NONE), + /* GP3 */ PAD_NC(GPP_B4, NONE), + /* SX EXIT */ PAD_NC(GPP_H3, NONE), + /* VID 0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* VID 1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* + * Time + */ + /* SYNC 0 */ PAD_NC(GPP_H19, NONE), + /* SYNC 1 */ PAD_CFG_GPO(GPP_B14, 1, PLTRST), + + /* + * Image Clock + */ + /* OUT 0 */ PAD_NC(GPP_D4, NONE), + /* OUT 1 */ PAD_NC(GPP_H20, NONE), + /* OUT 2 */ PAD_NC(GPP_H21, NONE), + /* OUT 3 */ PAD_NC(GPP_H22, NONE), + /* OUT 4 */ PAD_CFG_GPO(GPP_H23, 0, DEEP), + + /* + * I2S + */ + /* MCLK1 */ PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP), + /* MCLK2 */ PAD_NC(GPP_F8, NONE), + + /* + * I2S 0 + */ + /* SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* SFRM */ PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* TXD */ PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* RXD */ PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* RST */ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* + * I2S 1 + */ + /* CLK */ PAD_CFG_GPO(GPP_A23, 0, PLTRST), + /* RXD */ PAD_CFG_GPO(GPP_R5, 0, PLTRST), + /* TXD */ PAD_CFG_GPO(GPP_R6, 1, PLTRST), + /* SFRM */ PAD_NC(GPP_R7, NONE), + + /* + * I2S 2 + */ + /* CLK */ PAD_NC(GPP_A7, NONE), + /* RXD */ PAD_NC(GPP_A10, NONE), + /* TXD */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), + /* SFRM */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + + /* + * I2S 3 + */ + /* CLK */ PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* RXD */ PAD_CFG_GPO(GPP_A14, 0, PLTRST), + /* TXD */ PAD_NC(GPP_A13, NONE), + /* SFRM */ PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + + /* + * Soundwire 0 + */ + /* CLK */ PAD_NC(GPP_S0, NONE), + /* DATA */ PAD_NC(GPP_S1, NONE), + + /* + * Soundwire 1 + */ + /* CLK */ PAD_NC(GPP_S2, NONE), + /* DATA */ PAD_NC(GPP_S3, NONE), + + /* + * Soundwire 2 + */ + /* CLK */ PAD_NC(GPP_S4, NONE), + /* DATA */ PAD_NC(GPP_S5, NONE), + + /* + * Soundwire 3 + */ + /* CLK */ PAD_NC(GPP_S6, NONE), + /* DATA */ PAD_NC(GPP_S7, NONE), + + /* NOT USED */ PAD_NC(GPP_T2, NONE), + /* NOT USED */ PAD_NC(GPP_T3, NONE), + /* NOT USED */ PAD_NC(GPP_U4, NONE), + /* NOT USED */ PAD_NC(GPP_U5, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/60123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a Gerrit-Change-Number: 60123 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/spi/spi-generic: document SPI_CNTRLR_DEDUCT_CMD_LEN better
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60122 ) Change subject: drivers/spi/spi-generic: document SPI_CNTRLR_DEDUCT_CMD_LEN better ...................................................................... drivers/spi/spi-generic: document SPI_CNTRLR_DEDUCT_CMD_LEN better This should make it a bit clearer what the differences between SPI_CNTRLR_DEDUCT_OPCODE_LEN and SPI_CNTRLR_DEDUCT_CMD_LEN and the corresponding functionality in spi_crop_chunk are. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I809adebb182fc0866b93372b5b486117176da388 --- M src/drivers/spi/spi-generic.c M src/include/spi-generic.h 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60122/1 diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 9796663..e6ec7bd 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -98,6 +98,10 @@ if (deduct_opcode_len) cmd_len--; + /* Subtract command length from useable buffer size. If + deduct_opcode_len is set, only subtract the number command bytes + after the opcode. If the adjusted cmd_len is larger than ctrlr_max + return 0 to inidicate an error. */ if (deduct_cmd_len) { if (ctrlr_max >= cmd_len) { ctrlr_max -= cmd_len; diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 77a3c09..acb22ec 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -111,7 +111,8 @@ enum { /* Deduct the command length from the spi_crop_chunk() calculation for - sizing a transaction. */ + sizing a transaction. If SPI_CNTRLR_DEDUCT_OPCODE_LEN is set, only + the bytes after the command byte will be deducted. */ SPI_CNTRLR_DEDUCT_CMD_LEN = 1 << 0, /* Remove the opcode size from the command length used in the spi_crop_chunk() calculation. Controllers which have a dedicated -- To view, visit https://review.coreboot.org/c/coreboot/+/60122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I809adebb182fc0866b93372b5b486117176da388 Gerrit-Change-Number: 60122 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/spi/spi-generic: fix edge case in spi_crop_chunk
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60121 ) Change subject: drivers/spi/spi-generic: fix edge case in spi_crop_chunk ...................................................................... drivers/spi/spi-generic: fix edge case in spi_crop_chunk In the case of deduct_cmd_len being set and the adjusted cmd_len >= ctrlr_max, ctrlr_max wasn't being adjusted and still had the value of ctrlr->max_xfer_size. Handle this edge case (which we should never run into) by setting ctrlr_max to 0 and printing a warning to the console. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9941b2947bb0a44dfae8ee69f509795dfb0cb241 --- M src/drivers/spi/spi-generic.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/60121/1 diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 116daf9..9796663 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -98,8 +98,14 @@ if (deduct_opcode_len) cmd_len--; - if (deduct_cmd_len && (ctrlr_max > cmd_len)) - ctrlr_max -= cmd_len; + if (deduct_cmd_len) { + if (ctrlr_max >= cmd_len) { + ctrlr_max -= cmd_len; + } else { + ctrlr_max = 0; + printk(BIOS_WARNING, "%s: Command longer than buffer\n", __func__); + } + } return MIN(ctrlr_max, buf_len); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9941b2947bb0a44dfae8ee69f509795dfb0cb241 Gerrit-Change-Number: 60121 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/spi/fch_spi_ctrl: improve printk messages
by Felix Held (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60120 ) Change subject: soc/amd/common/block/spi/fch_spi_ctrl: improve printk messages ...................................................................... soc/amd/common/block/spi/fch_spi_ctrl: improve printk messages Replace FCH_SC with FCH SPI in the printk messages to make those a bit clearer and also remove an unneeded line break in another printk call. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6ff02163e6a48a2cc8b7fe89b15826e154715d29 --- M src/soc/amd/common/block/spi/fch_spi_ctrl.c 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/60120/1 diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 33e1139..f790247 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -98,7 +98,7 @@ spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); if (wait_for_ready()) { - printk(BIOS_ERR, "FCH_SC Error: Timeout executing command\n"); + printk(BIOS_ERR, "FCH SPI Error: Timeout executing command\n"); return -1; } @@ -121,8 +121,7 @@ const uint8_t *bufout = dout; if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) - printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, - bytesin); + printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, bytesin); /* First byte is cmd which cannot be sent through FIFO */ cmd = bufout[0]; @@ -136,7 +135,7 @@ * and followed by other SPI commands. */ if (bytesout + bytesin > SPI_FIFO_DEPTH) { - printk(BIOS_WARNING, "FCH_SC: Too much to transfer, code error!\n"); + printk(BIOS_WARNING, "FCH SPI: Too much to transfer, code error!\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/60120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff02163e6a48a2cc8b7fe89b15826e154715d29 Gerrit-Change-Number: 60120 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2021