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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57668 )
Change subject: soc/intel/baytrail,denverton_ns: Call setup_lapic()
......................................................................
Patch Set 10: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57668/comment/2ded4944_855c583c
PS10, Line 7: soc/intel/baytrail,denverton_ns: Call setup_lapic()
I checked Braswell out of curiosity (the code for Bay Trail and Braswell is pretty similar) and saw that CB:29290 already added the `setup_lapic()` call. Would be nice to reference that commit here.
Patchset:
PS3:
> Thanks for reminding, I will take over this commit.
Seems to be done?
File src/soc/intel/denverton_ns/cpu.c:
https://review.coreboot.org/c/coreboot/+/57668/comment/a40276c9_accbfb96
PS10, Line 24: #include <cpu/x86/lapic.h>
nit: move between `#include <cpu/intel/common/common.h>` and `#include <device/device.h>`
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Hello Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60101
to look at the new patch set (#2).
Change subject: mb/google/brya/var/primus: Update thermal table for primus
......................................................................
mb/google/brya/var/primus: Update thermal table for primus
- Because primus have five sensors,we need to define 5 sensors.
BUG=b:200836803
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com>
Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d
---
M src/mainboard/google/brya/variants/primus/overridetree.cb
1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/60101/2
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Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59991 )
Change subject: mb/google/dedede/var/madoo: Generate new SPD ID for new memory parts
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
Ping Karthik. thanks!
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Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60100 )
Change subject: mb/google/brya/variants/brask: disabled autonomous GPIO power management
......................................................................
mb/google/brya/variants/brask: disabled autonomous GPIO power management
We found that the `Cr50 i2c TPM IRQ timeout!` error when the device
executed the reboot test even though we have updated the cr50
firmware to the 0.6.70. Besides, we also need to avoid the factory
power on issue when using the 0.3.22 cr50 firmware. So, we submitted
this patch to disable the gpio power management.
BUG=b:210540890
TEST=reboot 100 cycles without the error message.
Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5
Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org>
---
M src/mainboard/google/brya/variants/brask/overridetree.cb
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/60100/1
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index 63a683d..3d9e7b1 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -1,4 +1,14 @@
chip soc/intel/alderlake
+ # This disabled autonomous GPIO power management, otherwise
+ # old cr50 FW only supports short pulses; need to clarify
+ # the minimum PCH IRQ pulse width with Intel, b/180111628
+ register "gpio_override_pm" = "1"
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_3]" = "0"
+ register "gpio_pm[COMM_4]" = "0"
+ register "gpio_pm[COMM_5]" = "0"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
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Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59305 )
Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
Patch Set 26: -Code-Review
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Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
Patch Set 26: Code-Review+1
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Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60099 )
Change subject: mb/google/brya/var/vell: update overridetree for SSD setting
......................................................................
mb/google/brya/var/vell: update overridetree for SSD setting
Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics
BUG=b:208756696
TEST=emerge-brya coreboot
Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37
Signed-off-by: = <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/60099/1
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 839d610..2b06ff5 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -125,10 +125,10 @@
end
end
device ref pcie4_0 on
- # Enable CPU PCIE RP 1 using CLK 0
+ # Enable CPU PCIE RP 1 using CLK 3
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 1,
- .clk_src = 3,
+ .clk_src = 1,
}"
end
device ref cnvi_wifi on
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Robert Chen has uploaded a new patch set (#22) to the change originally created by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/59334 )
Change subject: mb/google/brya/var/vell: update memory settings
......................................................................
mb/google/brya/var/vell: update memory settings
DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility
GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3
GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7
GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/vell/Makefile.inc
A src/mainboard/google/brya/variants/vell/memory.c
2 files changed, 104 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59334/22
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