coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Remove extra highspeed pad configurations
by Kyösti Mälkki (Code Review) 14 Dec '21

14 Dec '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60092 ) Change subject: mb/teleplatforms/D4E4S16P8: Remove extra highspeed pad configurations ...................................................................... mb/teleplatforms/D4E4S16P8: Remove extra highspeed pad configurations The board uses SKU with 20 available lanes. Also the supporting code under soc/ does not even try to detect the SKU and never queries for the other listed options. Change-Id: I64a705ed3cb1d787031818e50c3f9dd8d7f1d8ed Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/teleplatforms/D4E4S16P8/hsio.c 1 file changed, 0 insertions(+), 463 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/60092/1 diff --git a/src/mainboard/teleplatforms/D4E4S16P8/hsio.c b/src/mainboard/teleplatforms/D4E4S16P8/hsio.c index e8e5c54..a3e1942 100644 --- a/src/mainboard/teleplatforms/D4E4S16P8/hsio.c +++ b/src/mainboard/teleplatforms/D4E4S16P8/hsio.c @@ -148,469 +148,6 @@ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 12 (pcie [0-7] sata [8-13,15] aspeed[14] usb [18,19]) */ - {BL_SKU_HSIO_12, - {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x2x2x2x2}, - {/* ME_FIA_MUX_CONFIG */ - {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE04) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE05) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE06) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE07) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE12) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE13) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE15) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE18) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, - - /* ME_FIA_SATA_CONFIG */ - {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE04) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE05) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE06) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE07) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE08) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE09) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE10) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE11) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE12) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE13) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE14) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE15) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE16) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE17) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE18) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE19)}, - - /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ - {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_7) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, - BL_FIA_PCIE_ROOT_PORT_7)} } }, - - /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */ - {BL_SKU_HSIO_10, - {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, - {/* ME_FIA_MUX_CONFIG */ - {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, - - /* ME_FIA_SATA_CONFIG */ - {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE04) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE05) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE06) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE07) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE08) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE09) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE10) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE11) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE12) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE13) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE14) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE15) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE16) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE17) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE18) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE19)}, - - /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ - {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_7) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_7)} } }, - - /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */ - {BL_SKU_HSIO_08, - {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, - {/* ME_FIA_MUX_CONFIG */ - {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, - - /* ME_FIA_SATA_CONFIG */ - {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE04) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE05) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE06) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE07) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE08) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE09) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE10) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE11) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE12) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE13) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE14) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE15) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE16) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE17) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE18) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE19)}, - - /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ - {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_7) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_7)} } }, - - /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */ - {BL_SKU_HSIO_06, - {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, - {/* ME_FIA_MUX_CONFIG */ - {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE09) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, - - /* ME_FIA_SATA_CONFIG */ - {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE04) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE05) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE06) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE07) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE08) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE09) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE10) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE11) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE12) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE13) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE14) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE15) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE16) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE17) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE18) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE19)}, - - /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ - {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_7) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_7)} } } }; size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) -- To view, visit https://review.coreboot.org/c/coreboot/+/60092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64a705ed3cb1d787031818e50c3f9dd8d7f1d8ed Gerrit-Change-Number: 60092 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Fix MRC_RW_CACHE
by Kyösti Mälkki (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60091 ) Change subject: soc/intel/denverton_ns: Fix MRC_RW_CACHE ...................................................................... soc/intel/denverton_ns: Fix MRC_RW_CACHE It is required to set WPD (Write Protect Disable) bit to make it possible to use MRC_RW_CACHE region with CACHE_MRC_SETTINGS=y. Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/denverton_ns/bootblock/bootblock.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/60091/1 diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index cb2503a..7f35123 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -12,6 +12,7 @@ #include <spi-generic.h> #include <stdint.h> #include <console/console.h> +#include <intelblocks/fast_spi.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -84,6 +85,7 @@ #if (CONFIG(CONSOLE_SERIAL)) early_uart_init(); #endif + fast_spi_early_init(DEFAULT_SPI_BASE); }; void bootblock_soc_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/60091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e Gerrit-Change-Number: 60091 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8
by Kyösti Mälkki (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Dmitry Ponamorev, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph, King Sumo. Kyösti Mälkki has uploaded a new patch set (#21) to the change originally created by Dmitry Ponamorev. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 ...................................................................... mb/teleplatforms/D4E4S16P8: Add new CRB teleplatforms/D4E4S16P8 These sources are to compile the coreboot firmware image for the teleplatforms D4E4S16P8 motherboard. The board is based on an Intel Atom C3758 processor. Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Signed-off-by: Dmitry Ponamorev <dponamorev(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/mainboard/teleplatforms/D4E4S16P8/Kconfig A src/mainboard/teleplatforms/D4E4S16P8/Kconfig.name A src/mainboard/teleplatforms/D4E4S16P8/Makefile.inc A src/mainboard/teleplatforms/D4E4S16P8/acpi/mainboard.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi/mainboard_pci_irqs.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi/platform.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi/thermal.asl A src/mainboard/teleplatforms/D4E4S16P8/acpi_tables.c A src/mainboard/teleplatforms/D4E4S16P8/board_info.txt A src/mainboard/teleplatforms/D4E4S16P8/devicetree.cb A src/mainboard/teleplatforms/D4E4S16P8/dsdt.asl A src/mainboard/teleplatforms/D4E4S16P8/hsio.c A src/mainboard/teleplatforms/D4E4S16P8/ramstage.c A src/mainboard/teleplatforms/D4E4S16P8/romstage.c A src/mainboard/teleplatforms/Kconfig A src/mainboard/teleplatforms/Kconfig.name 16 files changed, 1,703 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/57194/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 21 Gerrit-Owner: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Use common SMBus support code
by Kyösti Mälkki (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. Hello Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59469 to look at the new patch set (#2). Change subject: soc/intel/denverton_ns: Use common SMBus support code ...................................................................... soc/intel/denverton_ns: Use common SMBus support code Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/smbus.h 4 files changed, 6 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/59469/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513 Gerrit-Change-Number: 59469 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/baytrail,denverton_ns: Call setup_lapic()
by Kyösti Mälkki (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Arthur Heymans, Dmitry Ponamorev, Michał Żygowski, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph, King Sumo. Kyösti Mälkki has uploaded a new patch set (#10) to the change originally created by Dmitry Ponamorev. ( https://review.coreboot.org/c/coreboot/+/57668 ) Change subject: soc/intel/baytrail,denverton_ns: Call setup_lapic() ...................................................................... soc/intel/baytrail,denverton_ns: Call setup_lapic() A custom board with soc/intel/denverton_ns does not respond to the keyboard and does not boot from the sata/USB disks. Last post code 0x7b and the last line that is displayed at log from SeaBIOS is: All threads complete. The issue is gone when adding setup_lapic() call to configure EXTINT delivery of i8259 originated interrupts for the LAPIC. Replicate call from other soc/ and make the call for both BSP and AP CPUs. Signed-off-by: Dmitry Ponamorev <dponamorev(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d --- M src/soc/intel/baytrail/cpu.c M src/soc/intel/denverton_ns/cpu.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/57668/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/57668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d Gerrit-Change-Number: 57668 Gerrit-PatchSet: 10 Gerrit-Owner: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/vell: update overridetree
by Robert Chen (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Kevin Chiu, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Wisley Chen, Shon Wang. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59304 ) Change subject: mb/google/brya/var/vell: update overridetree ...................................................................... Patch Set 16: (1 comment) File src/mainboard/google/brya/variants/vell/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59304/comment/81b9d3c1_cc5f07e5 PS10, Line 146: 0 > 3 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaa910eb1c5584197907963781258035c668298e Gerrit-Change-Number: 59304 Gerrit-PatchSet: 16 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 03:36:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: chromeos: Add an elog for Chrome OS diagnostic boot
by Jack Rosenthal (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Yu-Ping Wu, Aaron Durbin. Jack Rosenthal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54948 ) Change subject: chromeos: Add an elog for Chrome OS diagnostic boot ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb675fc431d4c45e4f432b2d12cac6dcfb2d5e3a Gerrit-Change-Number: 54948 Gerrit-PatchSet: 9 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 03:36:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update overridetree
by Robert Chen (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Kevin Chiu, Paul Menzel, Robert Chen, Nick Vaccaro, Wisley Chen, Shon Wang. Robert Chen has uploaded a new patch set (#16) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/59304 ) Change subject: mb/google/brya/var/vell: update overridetree ...................................................................... mb/google/brya/var/vell: update overridetree Init basic override devicetree based on schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ibaa910eb1c5584197907963781258035c668298e Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/vell/overridetree.cb 2 files changed, 367 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/59304/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/59304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaa910eb1c5584197907963781258035c668298e Gerrit-Change-Number: 59304 Gerrit-PatchSet: 16 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add stylus probe for garage
by EricR Lai (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60073 ) Change subject: mb/google/brya/var/felwinter: Add stylus probe for garage ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60073/comment/b4613c29_9218883b PS1, Line 9: garage driver only attach to stylus sku. > suggestion: […] Done File src/mainboard/google/brya/variants/felwinter/overridetree.cb: https://review.coreboot.org/c/coreboot/+/60073/comment/0d15048d_9c410553 PS1, Line 9: PRSENT > `PRESENT` […] typo woops. -- To view, visit https://review.coreboot.org/c/coreboot/+/60073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06a2c125f2b5a73f9f7c27bf1b20ff8712664809 Gerrit-Change-Number: 60073 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 03:34:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add stylus probe for garage
by EricR Lai (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Nick Vaccaro. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60073 to look at the new patch set (#3). Change subject: mb/google/brya/var/felwinter: Add stylus probe for garage ...................................................................... mb/google/brya/var/felwinter: Add stylus probe for garage Felwinter has non-stylus sku. Add a FW_CONFIG field to indicate stylus presence and add a probe statement to the devicetree for the corresponding device. BUG=b:208937710 TEST=non-stylus doesn't register garage driver. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I06a2c125f2b5a73f9f7c27bf1b20ff8712664809 --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/60073/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06a2c125f2b5a73f9f7c27bf1b20ff8712664809 Gerrit-Change-Number: 60073 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021