coreboot-gerrit December 2021

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Change in coreboot[master]: google/trogdor: Enable Parade ps8640 edp bridge for pazquel
by Julius Werner (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Henry Sun, Paul Menzel, Yunlong Jia, Bob Moragues. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60130 ) Change subject: google/trogdor: Enable Parade ps8640 edp bridge for pazquel ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/mainboard/google/trogdor/mainboard.c: https://review.coreboot.org/c/coreboot/+/60130/comment/b6f66507_1af96644 PS3, Line 87: 0x4 > The other lines use no 0x? The other lines are comparisons, this is a bitwise operation. For bitwise operations we usually write things in hex (or BIT(2) or something) to make them easier to follow (of course for 0x4 it happens to be the same as in decimal, but I still prefer having the general consistency... using hex also gives the reader an extra hint that this is a bitwise operation and not like the others). -- To view, visit https://review.coreboot.org/c/coreboot/+/60130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6130ee00a0e6f469142f5416627e38c7b5076071 Gerrit-Change-Number: 60130 Gerrit-PatchSet: 3 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kelsey Wang <peihwang(a)qualcomm.corp-partner.google.com> Gerrit-CC: Patrick Chang <changp(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Comment-Date: Thu, 16 Dec 2021 18:43:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQ...
by Saurabh Mishra (Code Review) 16 Dec '21

16 Dec '21

Saurabh Mishra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60170 ) Change subject: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/60170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570c1 Gerrit-Change-Number: 60170 Gerrit-PatchSet: 2 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQ...
by Saurabh Mishra (Code Review) 16 Dec '21

16 Dec '21

Saurabh Mishra has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/60176 ) Change subject: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. src/soc/intel/alderlake/fsp_params.c : Commented out the call. Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/60176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c573b1 Gerrit-Change-Number: 60176 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQ...
by Saurabh Mishra (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Tim Wawrzynczak. Saurabh Mishra has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/60176 ) Change subject: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. src/soc/intel/alderlake/fsp_params.c : Commented out the call. Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/60176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c573b1 Gerrit-Change-Number: 60176 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: drivers/i2c/generic: Print error when using _CRS and PowerResource
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Tim Crawford, Raul Rangel, Matt DeVillier, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60174 ) Change subject: drivers/i2c/generic: Print error when using _CRS and PowerResource ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: and others who use drivers/i2c/hid which borrows from this one -- To view, visit https://review.coreboot.org/c/coreboot/+/60174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84 Gerrit-Change-Number: 60174 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 16 Dec 2021 18:30:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQ...
by Saurabh Mishra (Code Review) 16 Dec '21

16 Dec '21

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60176 ) Change subject: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. src/soc/intel/alderlake/fsp_params.c : Commented out the call. Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. ...................................................................... src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. src/soc/intel/alderlake/fsp_params.c : Commented out the call. Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. change-Id: I0c6ae72610da39fc18ff252c440d006e83c573b1 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/meminit.c 2 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/60176/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 251b252..5d8559b 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -642,7 +642,7 @@ for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); - s_cfg->LpmStateEnableMask = get_supported_lpm_mask(); + //s_cfg->LpmStateEnableMask = get_supported_lpm_mask(); /* Apply minimum assertion width settings */ if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT) diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index d81e856..026bdcc 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -123,14 +123,14 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) { uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { - [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, - [1] = { &mem_cfg->MemorySpdPtr002, &mem_cfg->MemorySpdPtr003, }, - [2] = { &mem_cfg->MemorySpdPtr004, &mem_cfg->MemorySpdPtr005, }, - [3] = { &mem_cfg->MemorySpdPtr006, &mem_cfg->MemorySpdPtr007, }, - [4] = { &mem_cfg->MemorySpdPtr008, &mem_cfg->MemorySpdPtr009, }, - [5] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, - [6] = { &mem_cfg->MemorySpdPtr012, &mem_cfg->MemorySpdPtr013, }, - [7] = { &mem_cfg->MemorySpdPtr014, &mem_cfg->MemorySpdPtr015, }, + [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, }, + [1] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, }, + [2] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, }, + [3] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, }, + [4] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, }, + [5] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr010, }, + [6] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr010, }, + [7] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr010, }, }; uint8_t *disable_channel_upds[MRC_CHANNELS] = { &mem_cfg->DisableMc0Ch0, @@ -183,10 +183,10 @@ &mem_cfg->DqMapCpu2DramMc0Ch1, &mem_cfg->DqMapCpu2DramMc0Ch2, &mem_cfg->DqMapCpu2DramMc0Ch3, - &mem_cfg->DqMapCpu2DramMc0Ch4, - &mem_cfg->DqMapCpu2DramMc0Ch5, - &mem_cfg->DqMapCpu2DramMc0Ch6, - &mem_cfg->DqMapCpu2DramMc0Ch7, + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch0, }; const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0); @@ -204,10 +204,10 @@ &mem_cfg->DqsMapCpu2DramMc0Ch1, &mem_cfg->DqsMapCpu2DramMc0Ch2, &mem_cfg->DqsMapCpu2DramMc0Ch3, - &mem_cfg->DqsMapCpu2DramMc0Ch4, - &mem_cfg->DqsMapCpu2DramMc0Ch5, - &mem_cfg->DqsMapCpu2Drammc0Ch6, - &mem_cfg->DqsMapCpu2DramMc0Ch7, + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch0, }; const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0); -- To view, visit https://review.coreboot.org/c/coreboot/+/60176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c573b1 Gerrit-Change-Number: 60176 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/generic: Print error when using _CRS and PowerResource
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60174 ) Change subject: drivers/i2c/generic: Print error when using _CRS and PowerResource ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: see if kramasub@ has something to say -- To view, visit https://review.coreboot.org/c/coreboot/+/60174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84 Gerrit-Change-Number: 60174 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 16 Dec 2021 18:29:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Raul Rangel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60175 ) Change subject: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: I don't have time to deal with N bugs later 😋 so I'll fix these now. -- To view, visit https://review.coreboot.org/c/coreboot/+/60175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Gerrit-Change-Number: 60175 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Dec 2021 18:28:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Tim Wawrzynczak has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/60175 ) Change subject: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees ...................................................................... mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb 13 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/60175/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Gerrit-Change-Number: 60175 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Tim Wawrzynczak has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/60175 ) Change subject: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees ...................................................................... mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/ +/main:src/third_party/kernel/upstream/drivers/input/touchscreen/ elants_i2c.c;l=1429) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb 13 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/60175/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Gerrit-Change-Number: 60175 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021