coreboot-gerrit December 2021

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60183 ) Change subject: soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs ...................................................................... soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs The PMC IPC method that is used for RTD3 support expects to be provided the virtual wire index instead of the LCAP PN for CPU PCIe RPs. Therefore, use the prior patches to update pcie_rp for CPU RPs. BUG=b:197983574 TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and inspect the SSDT to see the PMC IPC parameters are as expected for the CPU RP, and the ModPhy power gating code is not found in the AML for the PEG port. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 20 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/60183/1 diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 507c3c8..a23dbb8 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -173,8 +173,7 @@ } static void -pcie_rtd3_acpi_method_status(int pcie_rp, - const struct soc_intel_common_block_pcie_rtd3_config *config) +pcie_rtd3_acpi_method_status(const struct soc_intel_common_block_pcie_rtd3_config *config) { const struct acpi_gpio *gpio; @@ -243,7 +242,7 @@ FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_ENTRY, 1), FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_DETECT, 1), }; - uint8_t pcie_rp; + int pcie_rp; struct acpi_dp *dsd, *pkg; if (!is_dev_enabled(parent)) { @@ -266,15 +265,25 @@ } const enum pcie_rp_type rp_type = soc_get_pcie_rp_type(parent); - - /* Read port number of root port that this device is attached to. */ - pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN); - if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { - printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp); + if (rp_type == PCIE_RP_PCH) { + /* Read port number of root port that this device is attached to. */ + pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN); + if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { + printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp); + return; + } + /* Port number is 1-based, PMC IPC method expects 0-based. */ + pcie_rp--; + } else if (rp_type == PCIE_RP_CPU) { + pcie_rp = soc_get_cpu_rp_vw_idx(parent); + if (pcie_rp < 0) { + printk(BIOS_ERR, "%s: Invalid CPU root port number\n", __func__); + return; + } + } else { + printk(BIOS_ERR, "%s: Unknown PCIe RP\n", __func__); return; } - /* Port number is 1-based, PMC IPC method expects 0-based. */ - pcie_rp--; printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), config->desc ?: dev->chip_ops->name); @@ -304,7 +313,7 @@ /* ACPI Power Resource for controlling the attached device power. */ acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); - pcie_rtd3_acpi_method_status(pcie_rp, config); + pcie_rtd3_acpi_method_status(config); pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); acpigen_pop_len(); /* PowerResource */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 Gerrit-Change-Number: 60183 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60182 ) Change subject: soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs ...................................................................... soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe ports, but the UPDs are not set. This patch hooks up those config structs to the appropriate FSP-S UPDs. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/60182/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 251b252..56e7d9a 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -615,6 +615,24 @@ } } +static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + const uint32_t enable_mask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); + for (int i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + if (!(enable_mask & BIT(i))) + continue; + + const struct pcie_rp_config *rp_cfg = &config->cpu_pcie_rp[i]; + s_cfg->CpuPcieRpL1Substates[i] = + get_l1_substate_control(rp_cfg->PcieRpL1Substates); + s_cfg->CpuPcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); + s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); + s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); + s_cfg->PtmEnabled[i] = 0; + } +} + static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { @@ -783,6 +801,7 @@ fill_fsps_pm_timer_params, fill_fsps_storage_params, fill_fsps_pcie_params, + fill_fsps_cpu_pcie_params, fill_fsps_misc_power_params, fill_fsps_irq_params, fill_fsps_fivr_params, -- To view, visit https://review.coreboot.org/c/coreboot/+/60182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927 Gerrit-Change-Number: 60182 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add minimal ACPI support for PEG ports
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60181 ) Change subject: soc/intel/alderlake: Add minimal ACPI support for PEG ports ...................................................................... soc/intel/alderlake: Add minimal ACPI support for PEG ports Add minimal Device entries with just an _ADR for each of the PEG ports for P and M chipsets (N does not have any PEG ports). Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468 --- M src/soc/intel/alderlake/acpi/pcie.asl M src/soc/intel/alderlake/chip.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/60181/1 diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl index a19feb7..f2123aa 100644 --- a/src/soc/intel/alderlake/acpi/pcie.asl +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -299,3 +299,22 @@ Return (IRQM (RPPN)) } } + +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) +Device (PEG0) +{ + Name (_ADR, 0x00060000) +} +#endif + +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) +Device (PEG1) +{ + Name (_ADR, 0x00060002) +} + +Device (PEG2) +{ + Name (_ADR, 0x00010000) +} +#endif diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index ae28d18..1fa78fb 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -61,6 +61,9 @@ switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_CPU_PCIE1_0: return "PEG2"; + case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; + case SA_DEVFN_CPU_PCIE6_2: return "PEG1"; case SA_DEVFN_IGD: return "GFX0"; case SA_DEVFN_TCSS_XHCI: return "TXHC"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; -- To view, visit https://review.coreboot.org/c/coreboot/+/60181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468 Gerrit-Change-Number: 60181 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60180 ) Change subject: soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function ...................................................................... soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function The PMC IPC method used to enable/disable PCIe srcclks uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147 --- M src/soc/intel/alderlake/pcie_rp.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/60180/1 diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index dd0cfbc..26ce785 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -6,6 +6,8 @@ #include <soc/pci_devs.h> #include <soc/pcie.h> +#define CPU_CPIE_VW_IDX_BASE 24 + static const struct pcie_rp_group pch_lp_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, @@ -91,3 +93,20 @@ return PCIE_RP_UNKNOWN; } + +int soc_get_cpu_rp_vw_idx(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return -1; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_CPU_PCIE1_0: + return CPU_CPIE_VW_IDX_BASE; + case SA_DEVFN_CPU_PCIE6_0: + return CPU_CPIE_VW_IDX_BASE + 3; + case SA_DEVFN_CPU_PCIE6_2: + return CPU_CPIE_VW_IDX_BASE + 2; + default: + return -1; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147 Gerrit-Change-Number: 60180 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60179 ) Change subject: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function ...................................................................... soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function The PMC IPC method used to enable/disable PCIe srcclks uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d --- M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/tigerlake/pcie_rp.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/60179/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index ff10c51..f5ed892 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -121,4 +121,7 @@ struct device; /* Not necessary to include all of device/device.h */ enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev); +/* Return the virtual wire index that represents CPU-side PCIe root ports */ +int soc_get_cpu_rp_vw_idx(const struct device *dev); + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c index a9a6c7f..b543d9a 100644 --- a/src/soc/intel/tigerlake/pcie_rp.c +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -49,3 +49,22 @@ return PCIE_RP_UNKNOWN; } + +int soc_get_cpu_rp_vw_idx(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return -1; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_PEG1: + return CPU_CPIE_VW_IDX_BASE + 2; + case SA_DEVFN_PEG2: + return CPU_CPIE_VW_IDX_BASE + 1; + case SA_DEVFN_PEG1: + return CPU_CPIE_VW_IDX_BASE; + case SA_DEVFN_CPU_PCIE: + return CPU_CPIE_VW_IDX_BASE + 3; + default: + return -1; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/60179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Gerrit-Change-Number: 60179 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/generic: Print error when using _CRS and PowerResource
by Matt DeVillier (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Tim Crawford, Raul Rangel, Karthik Ramasubramanian. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60174 ) Change subject: drivers/i2c/generic: Print error when using _CRS and PowerResource ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > The choice should be mutually exclusive. […] agreed, thx for the clarification -- To view, visit https://review.coreboot.org/c/coreboot/+/60174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84 Gerrit-Change-Number: 60174 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 16 Dec 2021 22:03:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add -Wno-address-of-packed-member for ARCH_MOCK
by Julius Werner (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60169 ) Change subject: libpayload: Add -Wno-address-of-packed-member for ARCH_MOCK ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a948fabe66f7297632ecaca8ec1bfa5c842b750 Gerrit-Change-Number: 60169 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 16 Dec 2021 22:01:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: do not lock GPP_B16/ GPP_B17
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Nick Vaccaro, Scott Chao, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60126 ) Change subject: soc/intel/alderlake: do not lock GPP_B16/ GPP_B17 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hmm, something seems fishy here, I thought these were reset on warm reboot. For the meantime, instead of this (because maybe it's causing other problems too), let's just remove `SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS` from soc/intel/alderlake/Kconfig instead of removing GPIOs piecemeal. -- To view, visit https://review.coreboot.org/c/coreboot/+/60126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I106ddc96c3185656d3f1fbcd45f198d2d46f3f4d Gerrit-Change-Number: 60126 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 16 Dec 2021 21:01:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add timestamp for cse_fw_sync
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60135 ) Change subject: soc/intel/alderlake: Add timestamp for cse_fw_sync ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60135/comment/44cd991a_79665ac6 PS2, Line 13: 7 missing `)` at the end -- To view, visit https://review.coreboot.org/c/coreboot/+/60135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Gerrit-Change-Number: 60135 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 16 Dec 2021 20:58:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "security/vboot: Add NVRAM counter for TPM 2.0"
by Raul Rangel (Code Review) 16 Dec '21

16 Dec '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60030 ) Change subject: Revert "security/vboot: Add NVRAM counter for TPM 2.0" ...................................................................... Revert "security/vboot: Add NVRAM counter for TPM 2.0" This reverts commit 7dce19080889955576f8fd197658077aced96a96. Reason for revert: Unable to boot in factory mode Change-Id: I1b51010080164c6e28d77a932f77c10006fd4153 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60030 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/security/vboot/antirollback.h M src/security/vboot/secdata_tpm.c 2 files changed, 0 insertions(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 71605fa..75bfcdc 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -28,7 +28,6 @@ /* 0x100d: Hash of MRC_CACHE training data for non-recovery boot */ #define MRC_RW_HASH_NV_INDEX 0x100d #define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE -#define ENT_ROLLBACK_COUNTER_INDEX 0x100e /* Widevine Secure Counter space */ #define WIDEVINE_COUNTER_NV_INDEX(n) (0x3000 + (n)) #define NUM_WIDEVINE_COUNTERS 4 diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 6d8e281..847a959 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -116,17 +116,6 @@ .TPMA_NV_WRITE_STCLEAR = 1, }; -const static TPMA_NV rw_counter_attributes = { - .TPMA_NV_AUTHWRITE = 1, - .TPMA_NV_AUTHREAD = 1, - .TPMA_NV_PPREAD = 1, - .TPMA_NV_PPWRITE = 1, - .TPMA_NV_PLATFORMCREATE = 1, - .TPMA_NV_COUNTER = 1, - .TPMA_NV_NO_DA = 1, - .TPMA_NV_WRITE_STCLEAR = 1, -}; - static const TPMA_NV fwmp_attr = { .TPMA_NV_PLATFORMCREATE = 1, .TPMA_NV_OWNERWRITE = 1, @@ -353,15 +342,6 @@ return rv; } -static uint32_t enterprise_rollback_create_counter(void) -{ - /* - * No need to increment the counter to initialize, this can be done later. - */ - return tlcl_define_space(ENT_ROLLBACK_COUNTER_INDEX, /*size=*/8, - rw_counter_attributes, NULL, 0); -} - static uint32_t setup_widevine_counter_spaces(void) { uint32_t index, rv; @@ -408,14 +388,6 @@ CONFIG(MAINBOARD_HAS_I2C_TPM_CR50)))) RETURN_ON_FAILURE(setup_zte_spaces()); - /* - * On TPM 2.0, create a counter that survives TPM clear. This allows to - * securely lock data during enterprise rollback by binding to this - * counter's value. - */ - if (CONFIG(CHROMEOS)) - RETURN_ON_FAILURE(enterprise_rollback_create_counter()); - /* Define widevine counter space. No need to increment/write to the secure counters and are expected to be incremented during the first use. */ if (CONFIG(VBOOT_DEFINE_WIDEVINE_COUNTERS)) -- To view, visit https://review.coreboot.org/c/coreboot/+/60030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b51010080164c6e28d77a932f77c10006fd4153 Gerrit-Change-Number: 60030 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Miriam Polzer <mpolzer(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021