YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59749 )
Change subject: mb/google/brya/var/taeko: Set vGPIO reset type
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Please sync the change to taeko4es if applicable. […]
Ping!! Please apply the same change for taeko4es if applicable -- which looks to be the case?
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Change subject: drivers/i2c/generic: Print error when using _CRS and PowerResource
......................................................................
Removed Code-Review+2 by Raul Rangel <rrangel(a)chromium.org>
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Hello Tim Crawford, build bot (Jenkins), Matt DeVillier, Tim Wawrzynczak, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60174
to look at the new patch set (#2).
Change subject: drivers/i2c/generic: Print error when using _CRS and PowerResource
......................................................................
drivers/i2c/generic: Print error when using _CRS and PowerResource
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO. I'm making this an error because we should really clean these up.
BUG=b:210694108
TEST=Boot guybrush and see error:
> I2C: 02:5d: ERROR: Exposing GPIOs in Power Resource and _CRS
> \_SB.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84
---
M src/drivers/i2c/generic/generic.c
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60174/2
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs
......................................................................
soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe
ports, but the UPDs are not set. This patch hooks up those config
structs to the appropriate FSP-S UPDs.
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---
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Change subject: mb/google/brya/var/brask: Add wake-on-lan function
......................................................................
Patch Set 1: Code-Review+2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60106 )
Change subject: mb/google/brya/var/vell: Swap TPM I2C with touchscreen I2C
......................................................................
Patch Set 3: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60106/comment/ec36fff3_bb57ca9e
PS3, Line 9: latest schematic,
`latest schematic for the next build phase`
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/60106/comment/117c4785_5a82c120
PS1, Line 93: BOARD_GOOGLE_VELL4ES
> Done
Done
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60143 )
Change subject: drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointers
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60143/comment/54eac537_2aab104b
PS2, Line 14: e.g
nit:
`i.e.`
Patchset:
PS2:
Thanks, this one's been bugging me for a while!
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Change subject: soc/intel/common: Do not trigger crashlog on all resets by default
......................................................................
Patch Set 6: Code-Review+2
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