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Change subject: soc/intel/jsl: Add CdClock config
......................................................................
soc/intel/jsl: Add CdClock config
This dev tree config controls the CdClock for Jasperlake.
BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
3 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/8
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Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
Patch Set 47: Verified+1
(1 comment)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135697):
https://review.coreboot.org/c/coreboot/+/57131/comment/2e1d4a7c_5a734cfd
PS47, Line 1892: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER);
line over 96 characters
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Change subject: amdfwtool: Add ISH header support for A/B recovery layout
......................................................................
Patch Set 38: Verified+1
(1 comment)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135695):
https://review.coreboot.org/c/coreboot/+/57747/comment/71c99127_39beb16e
PS38, Line 696: pspdir->entries[count].addr = BUFF_TO_RUN_MODE(*ctx, ish, ADDRESS_MODE_1_REL_BIOS);
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Change subject: soc/intel/jsl: Add CdClock/SkipCdClockInit config
......................................................................
Patch Set 7:
(1 comment)
This change is ready for review.
File src/soc/intel/jasperlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/60009/comment/24d0b891_2340ca6b
PS6, Line 212: if (config->SkipCdClockInit) {
> braces {} are not necessary for single statement blocks
fixed
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Change subject: util/crossgcc: Update binutils to 2.37
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
> What this error means […]
If you run `make V=1` it should show you the command line that results in this
error. Also, can you tell us what version (commit hash) of coreboot you are
using and the xgcc version?
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Change subject: mb/google/brya/variants/primus: remove board_id check for ALC5682I-VS
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60128/comment/6bb22df7_c1523d13
PS2, Line 9: The board ID check for audio codec is no longer required, therefore
: remove it.
> Why is it not required anymore?
In each subsequent phase build, it is possible to import RT5682I-VD and RT5682I-VS codec at the same time, so only use fw_config to distinguish without using board_id.
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Change subject: mb/google/guybrush/dewatt: update DRAM ID table
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt:
https://review.coreboot.org/c/coreboot/+/60090/comment/c5dfa375_216e4e58
PS1, Line 10: K4UBE3D4AB-MGCL
> Please append only in this file.
Thanks. Done.
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Hello build bot (Jenkins), Bhanu Prakash Maiya, Rob Barnes,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/guybrush/dewatt: update DRAM ID table
......................................................................
mb/google/guybrush/dewatt: update DRAM ID table
Samsung LPDDR4X 4266 4G K4UBE3D4AB-MGCL
BUG=b:203014978
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com>
Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed
---
M src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc
M src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt
M src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt
3 files changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/60090/2
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