coreboot-gerrit December 2021

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Change in coreboot[master]: lib: Add a mutex
by Kyösti Mälkki (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Raul Rangel, Julius Werner, Rob Barnes, Karthik Ramasubramanian. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 13: (3 comments) Patchset: PS13: I won't be able to +1 this. This really adds a spinlock implementation with .bss while keeping the spinlock implementation in .data around. Also, I feel this uses 3x the lines of code it should, follow-ups extend unnecessarily (and mostly without argumentation) to existing uses of spinlock, and I am not convinced this brings much DMA performance to romstage if the DMA thread is almost never serviced. File src/lib/mutex.c: https://review.coreboot.org/c/coreboot/+/59320/comment/0c14dc26_1248d055 PS13, Line 16: } What makes the two above a mutex and not a spinlock? Your struct mutex is really nothing more but a new spinlock implementation with .bss. It only becomes a mutex when these get used with the possibility to yield. https://review.coreboot.org/c/coreboot/+/59320/comment/2cfe7b0a_7d54d90d PS13, Line 43: assert(_mutex_is_locked_smp(mutex)); Do we allow uses of assert() with side-effects? Like commented before, the printk() here (which one should never hit) kills romstage DMA performance as you need to disable coop while in printk. IMHO it should be allowed to have empty ASSERT() definition. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 13 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 17 Dec 2021 05:35:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy: Drop unnecessary Kconfig options
by Felix Singer (Code Review) 17 Dec '21

17 Dec '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60189 ) Change subject: mb/google/poppy: Drop unnecessary Kconfig options ...................................................................... mb/google/poppy: Drop unnecessary Kconfig options Change-Id: I0eb3fdc4fd7306e76d5479494e3ab80bbdb984fe Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/poppy/Kconfig 1 file changed, 54 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/60189/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index dce2ecc..b938ed7 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -19,31 +19,78 @@ config BOARD_GOOGLE_ATLAS select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_ATLAS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_MAX98373 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_SPI_TPM_CR50 + select SYSTEM_TYPE_LAPTOP + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_POPPY select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_POPPY + select DRIVERS_I2C_MAX98927 + select MAINBOARD_HAS_I2C_TPM_CR50 + select NO_FADT_8042 + select SYSTEM_TYPE_LAPTOP + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_NAMI select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAMI + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select MAINBOARD_HAS_SPI_TPM_CR50 + select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_NAUTILUS select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAUTILUS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select MAINBOARD_HAS_I2C_TPM_CR50 + select SYSTEM_TYPE_CONVERTIBLE + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_NOCTURNE select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NOCTURNE + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_SX9310 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select MAINBOARD_HAS_SPI_TPM_CR50 + select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_RAMMUS select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_RAMMUS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_MAX98927 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_SPI_TPM_CR50 + select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_SORAKA select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_SORAKA + select DRIVERS_I2C_MAX98927 + select MAINBOARD_HAS_I2C_TPM_CR50 + select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE + select VARIANT_HAS_CAMERA_ACPI if BOARD_GOOGLE_BASEBOARD_POPPY @@ -155,81 +202,6 @@ bool default n -config VARIANT_SPECIFIC_OPTIONS_ATLAS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_DA7219 - select DRIVERS_I2C_MAX98373 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_SPI_TPM_CR50 - select SYSTEM_TYPE_LAPTOP - select VARIANT_HAS_CAMERA_ACPI - -config VARIANT_SPECIFIC_OPTIONS_POPPY - def_bool n - select DRIVERS_I2C_MAX98927 - select MAINBOARD_HAS_I2C_TPM_CR50 - select NO_FADT_8042 - select SYSTEM_TYPE_LAPTOP - select VARIANT_HAS_CAMERA_ACPI - -config VARIANT_SPECIFIC_OPTIONS_NAMI - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select MAINBOARD_HAS_SPI_TPM_CR50 - select SYSTEM_TYPE_LAPTOP - -config VARIANT_SPECIFIC_OPTIONS_NAUTILUS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - select MAINBOARD_HAS_I2C_TPM_CR50 - select SYSTEM_TYPE_CONVERTIBLE - select VARIANT_HAS_CAMERA_ACPI - -config VARIANT_SPECIFIC_OPTIONS_NOCTURNE - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_DA7219 - select DRIVERS_I2C_MAX98373 - select DRIVERS_I2C_SX9310 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR - select MAINBOARD_HAS_SPI_TPM_CR50 - select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE - select VARIANT_HAS_CAMERA_ACPI - -config VARIANT_SPECIFIC_OPTIONS_RAMMUS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_DA7219 - select DRIVERS_I2C_MAX98927 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_SPI_TPM_CR50 - select SYSTEM_TYPE_LAPTOP - -config VARIANT_SPECIFIC_OPTIONS_SORAKA - def_bool n - select DRIVERS_I2C_MAX98927 - select MAINBOARD_HAS_I2C_TPM_CR50 - select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE - select VARIANT_HAS_CAMERA_ACPI - config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE -- To view, visit https://review.coreboot.org/c/coreboot/+/60189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eb3fdc4fd7306e76d5479494e3ab80bbdb984fe Gerrit-Change-Number: 60189 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy: Move selects from Kconfig.name to Kconfig
by Felix Singer (Code Review) 17 Dec '21

17 Dec '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60188 ) Change subject: mb/google/poppy: Move selects from Kconfig.name to Kconfig ...................................................................... mb/google/poppy: Move selects from Kconfig.name to Kconfig Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I462426f2ef4a0ff62c0a7c1eb2a4946fba68c4a9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/Kconfig.name 2 files changed, 28 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/60188/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 462b694..dce2ecc 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -17,6 +17,34 @@ select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE +config BOARD_GOOGLE_ATLAS + select BOARD_GOOGLE_BASEBOARD_POPPY + select VARIANT_SPECIFIC_OPTIONS_ATLAS + +config BOARD_GOOGLE_POPPY + select BOARD_GOOGLE_BASEBOARD_POPPY + select VARIANT_SPECIFIC_OPTIONS_POPPY + +config BOARD_GOOGLE_NAMI + select BOARD_GOOGLE_BASEBOARD_POPPY + select VARIANT_SPECIFIC_OPTIONS_NAMI + +config BOARD_GOOGLE_NAUTILUS + select BOARD_GOOGLE_BASEBOARD_POPPY + select VARIANT_SPECIFIC_OPTIONS_NAUTILUS + +config BOARD_GOOGLE_NOCTURNE + select BOARD_GOOGLE_BASEBOARD_POPPY + select VARIANT_SPECIFIC_OPTIONS_NOCTURNE + +config BOARD_GOOGLE_RAMMUS + select BOARD_GOOGLE_BASEBOARD_POPPY + select VARIANT_SPECIFIC_OPTIONS_RAMMUS + +config BOARD_GOOGLE_SORAKA + select BOARD_GOOGLE_BASEBOARD_POPPY + select VARIANT_SPECIFIC_OPTIONS_SORAKA + if BOARD_GOOGLE_BASEBOARD_POPPY config CHROMEOS_WIFI_SAR diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name index fe0dd17..4b1fe69 100644 --- a/src/mainboard/google/poppy/Kconfig.name +++ b/src/mainboard/google/poppy/Kconfig.name @@ -2,18 +2,12 @@ config BOARD_GOOGLE_ATLAS bool "-> Atlas (Google Pixelbook Go)" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_ATLAS config BOARD_GOOGLE_POPPY bool "-> Poppy" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_POPPY config BOARD_GOOGLE_NAMI bool "-> Nami" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAMI help The Nami board supports the following devices: - Acer Chromebook 13 / Spin 13 (Akali) @@ -24,18 +18,12 @@ config BOARD_GOOGLE_NAUTILUS bool "-> Nautilus (Samsung Chromebook Plus V2, V2 LTE)" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAUTILUS config BOARD_GOOGLE_NOCTURNE bool "-> Nocturne (Google Pixel Slate)" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NOCTURNE config BOARD_GOOGLE_RAMMUS bool "-> Rammus" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_RAMMUS help The Rammus board supports the following devices: - Asus Chromebook C425 (Leona) @@ -43,5 +31,3 @@ config BOARD_GOOGLE_SORAKA bool "-> Soraka (HP Chromebook x2)" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_SORAKA -- To view, visit https://review.coreboot.org/c/coreboot/+/60188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I462426f2ef4a0ff62c0a7c1eb2a4946fba68c4a9 Gerrit-Change-Number: 60188 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy: Restore alphabetical order on Kconfig selects
by Felix Singer (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60144 to look at the new patch set (#2). Change subject: mb/google/poppy: Restore alphabetical order on Kconfig selects ...................................................................... mb/google/poppy: Restore alphabetical order on Kconfig selects Change-Id: If5cb98712767e2acab8955931d4f342c8f3d7824 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/poppy/Kconfig 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/60144/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5cb98712767e2acab8955931d4f342c8f3d7824 Gerrit-Change-Number: 60144 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/taeko4es: Fix PLD group order (W/A)
by YH Lin (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Joey Peng, Tim Wawrzynczak. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60187 ) Change subject: mb/google/brya/var/taeko4es: Fix PLD group order (W/A) ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: This is carry-over from the taeko variant (per https://review.coreboot.org/c/coreboot/+/59973). -- To view, visit https://review.coreboot.org/c/coreboot/+/60187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 Gerrit-Change-Number: 60187 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 17 Dec 2021 05:00:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko4es: Set vGPIO reset type
by YH Lin (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Joey Peng, Tim Wawrzynczak. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60186 ) Change subject: mb/google/brya/var/taeko4es: Set vGPIO reset type ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: This is carry-over from the taeko variant (per https://review.coreboot.org/c/coreboot/+/59749). -- To view, visit https://review.coreboot.org/c/coreboot/+/60186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782 Gerrit-Change-Number: 60186 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 17 Dec 2021 04:59:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko4es: Fix PLD group order (W/A)
by Joey Peng (Code Review) 17 Dec '21

17 Dec '21

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60187 ) Change subject: mb/google/brya/var/taeko4es: Fix PLD group order (W/A) ...................................................................... mb/google/brya/var/taeko4es: Fix PLD group order (W/A) In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table") BUG=b:209723556 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 --- M src/mainboard/google/brya/variants/taeko4es/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/60187/1 diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index d485662..ff4feef 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -443,7 +443,7 @@ chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A end @@ -463,7 +463,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A end -- To view, visit https://review.coreboot.org/c/coreboot/+/60187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 Gerrit-Change-Number: 60187 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/taeko4es: Set vGPIO reset type
by Joey Peng (Code Review) 17 Dec '21

17 Dec '21

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60186 ) Change subject: mb/google/brya/var/taeko4es: Set vGPIO reset type ...................................................................... mb/google/brya/var/taeko4es: Set vGPIO reset type Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207070967 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782 --- M src/mainboard/google/brya/variants/taeko4es/gpio.c 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/60186/1 diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c index 17018cd..aa778fc 100644 --- a/src/mainboard/google/brya/variants/taeko4es/gpio.c +++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c @@ -175,26 +175,26 @@ */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* CPU PCIe VGPIO for PEG60 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; const struct pad_config *variant_gpio_override_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/60186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782 Gerrit-Change-Number: 60186 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy/Kconfig: Restore alphabetical order on Kconfig selects
by Felix Singer (Code Review) 17 Dec '21

17 Dec '21

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60144 ) Change subject: mb/google/poppy/Kconfig: Restore alphabetical order on Kconfig selects ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/60144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5cb98712767e2acab8955931d4f342c8f3d7824 Gerrit-Change-Number: 60144 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 17 Dec 2021 04:39:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/acpimmio/print_reset_status: add missing status bit
by Raul Rangel (Code Review) 17 Dec '21

17 Dec '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60184 ) Change subject: soc/amd/common/block/acpimmio/print_reset_status: add missing status bit ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624 Gerrit-Change-Number: 60184 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 17 Dec 2021 03:50:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2021