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Change in coreboot[master]: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60175 ) Change subject: mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees ...................................................................... mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/ +/main:src/third_party/kernel/upstream/drivers/input/touchscreen/ elants_i2c.c;l=1429) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb 13 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/60175/1 diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index dc563a4..118ce0c 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -215,6 +215,7 @@ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end chip drivers/i2c/hid @@ -229,6 +230,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index dc563a4..118ce0c 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -215,6 +215,7 @@ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end chip drivers/i2c/hid @@ -229,6 +230,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index dafdbfc..9d2c61b 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -256,6 +256,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 4bfe124..3d8f52b 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -217,6 +217,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end end diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index 5d6d4fc..d0d54d7 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -173,6 +173,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end end diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index a908a7b..a4a5c54 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -425,6 +425,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x10 on end end diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 58c52a7..b9a1338 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -232,6 +232,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x10 on end end @@ -247,6 +248,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x40 on end end diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index 22d61b0..3cb5cdb 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -219,6 +219,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x10 on end end @@ -234,6 +235,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x40 on end end diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 617ebc5..5aa84bdc 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -386,6 +386,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end end diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 9531e5e..9ffc6a0 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -270,6 +270,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end end diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index ff4feef..985745f 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -292,6 +292,7 @@ # Parameter T4 >= 1ms register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end @@ -307,6 +308,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end end diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index d485662..dbca8ee 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -292,6 +292,7 @@ # Parameter T4 >= 1ms register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end @@ -307,6 +308,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end end diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index a65c859..483dce7 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -191,6 +191,7 @@ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end chip drivers/i2c/hid @@ -205,6 +206,7 @@ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Gerrit-Change-Number: 60175 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/acpi: Add support for RTC workaround
by Mario Limonciello (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Mario Limonciello has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60172 ) Change subject: soc/amd/cezanne/acpi: Add support for RTC workaround ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e Gerrit-Change-Number: 60172 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mario Limonciello <mario.limonciello(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 16 Dec 2021 18:07:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/generic: Print error when using _CRS and PowerResource
by Raul Rangel (Code Review) 16 Dec '21

16 Dec '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60174 ) Change subject: drivers/i2c/generic: Print error when using _CRS and PowerResource ...................................................................... drivers/i2c/generic: Print error when using _CRS and PowerResource Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. I'm making this an error because we should really clean these up. BUG=b: TEST=Boot guybrush and see error: > I2C: 02:5d: ERROR: Exposing GPIOs in Power Resource and _CRS > \_SB.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84 --- M src/drivers/i2c/generic/generic.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60174/1 diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 656b9e6..a993fe0 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -65,6 +65,16 @@ return; } + if (config->has_power_resource && !config->disable_gpio_export_in_crs) { + /* + * This case will most likely cause timing problems. The OS driver might be + * controlling the GPIOs, but the ACPI Power Resource will also be controlling + * them. This will result in the two fighting and stomping on each other. + */ + printk(BIOS_ERR, "%s: ERROR: Exposing GPIOs in Power Resource and _CRS\n", + dev_path(dev)); + } + /* Device */ acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); -- To view, visit https://review.coreboot.org/c/coreboot/+/60174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84 Gerrit-Change-Number: 60174 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Disable GPIO export for Goodix Touchscreen
by Raul Rangel (Code Review) 16 Dec '21

16 Dec '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60173 ) Change subject: mb/google/guybrush: Disable GPIO export for Goodix Touchscreen ...................................................................... mb/google/guybrush: Disable GPIO export for Goodix Touchscreen We want ACPI to own the GPIOs. This will stop the GPIOs from being exposed to the OS driver. BUG=b:209705576, b:210694108 TEST=Dump ACPI table and verify GPIO are no longer in _CRS. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b --- M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/60173/1 diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 01876c8..934fdbf 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -103,6 +103,7 @@ register "generic.stop_delay_ms" = "170" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b Gerrit-Change-Number: 60173 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/acpi: Add support for RTC workaround
by Raul Rangel (Code Review) 16 Dec '21

16 Dec '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60172 ) Change subject: soc/amd/cezanne/acpi: Add support for RTC workaround ...................................................................... soc/amd/cezanne/acpi: Add support for RTC workaround The RTC on Cezanne is an unstable wake source when the system is in S0i3. We instead need to use an internal timer that triggers a GPIO that acts as a wake source. This change provides the ACPI necessary to allow the OS to manage the wake source. BUG=b:209705576 TEST=Boot guybrush with this patch and several OS patches. Verified the OS sets the correct wake bit, the system correctly suspends and resumes, and the wake source is correctly accounted for. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e --- A src/soc/amd/cezanne/acpi/rtc_workaround.asl M src/soc/amd/cezanne/acpi/soc.asl 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/60172/1 diff --git a/src/soc/amd/cezanne/acpi/rtc_workaround.asl b/src/soc/amd/cezanne/acpi/rtc_workaround.asl new file mode 100644 index 0000000..e69e974 --- /dev/null +++ b/src/soc/amd/cezanne/acpi/rtc_workaround.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Workaround for RTC on Cezanne. + * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… + */ + +Scope (\_SB.PEP) { + Name (_PRW, Package () { + Package() {\_SB.GPIO, 0}, + 0x03 + }) +} + +Scope (\_SB.GPIO) { + Name (_AEI, ResourceTemplate () { + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, "\\_SB.GPIO",,,,) + { + 44 /* int_shdwsysalarmfire */ + } + }) + + Method (_E2C, 0, Serialized) { + Notify (\_SB_.PEP, 0x02) + } +} diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index e603307..bf2838a 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -27,6 +27,8 @@ #include <soc/amd/common/acpi/upep.asl> +#include "rtc_workaround.asl" + /* * Platform Wake Notify * -- To view, visit https://review.coreboot.org/c/coreboot/+/60172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e Gerrit-Change-Number: 60172 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE
by Raul Rangel (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60139 ) Change subject: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Gerrit-Change-Number: 60139 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 16 Dec 2021 17:40:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE
by Paul Menzel (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Rob Barnes, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60139 ) Change subject: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Gerrit-Change-Number: 60139 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 16 Dec 2021 17:37:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/brask: Disable autonomous GPIO power management
by Paul Menzel (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Zhuohao Lee. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60100 ) Change subject: mb/google/brya/variants/brask: Disable autonomous GPIO power management ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5 Gerrit-Change-Number: 60100 Gerrit-PatchSet: 5 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Dec 2021 17:35:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to devi...
by Tim Crawford (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Reka Norman, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60143 ) Change subject: drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointers ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Gerrit-Change-Number: 60143 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 16 Dec 2021 17:20:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQ...
by Saurabh Mishra (Code Review) 16 Dec '21

16 Dec '21

Saurabh Mishra has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/60170 ) Change subject: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. ...................................................................... src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. change-Id: I0c6ae72610da39fc18ff252c440d006e83c570c1 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/alderlake/meminit.c 1 file changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/60170/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570c1 Gerrit-Change-Number: 60170 Gerrit-PatchSet: 2 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2021