coreboot-gerrit December 2021

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Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
by Nico Huber (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 ) Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59918/comment/d13d5e73_1d362c88 PS5, Line 11: https://partnerissuetracker.corp.google.com/issues/203061533#comment6 > Done Ok, so the issue is private. Is the information too? Generally, it's preferred to repeat everything in the commit message (or coreboot documentation) that is necessary for review or otherwise interesting to the reviewer. The commit history stays forever, private bug trackers don't... -- To view, visit https://review.coreboot.org/c/coreboot/+/59918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Gerrit-Change-Number: 59918 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 16 Dec 2021 16:27:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/libc/fmap: Implement new FlashMap API
by Jakub Czapiga (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Julius Werner. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59494 ) Change subject: libpayload/libc/fmap: Implement new FlashMap API ...................................................................... Patch Set 9: (3 comments) Patchset: PS7: > Well, the patch is landed now so it should definitely be included in Jenkins builds. […] Ok, I know, what is happening here. coreinfo and nvramciu are using lpgcc, which does not pass commonlib/bsd include paths to GCC. Can you take a look at the potential fix? -> CB:60171 File payloads/libpayload/tests/libc/fmap_locate_area-test.c: https://review.coreboot.org/c/coreboot/+/59494/comment/085536cb_2598874e PS6, Line 98: _fmap_cache = NULL; > Hmm... yeah... why does it call free() anyway? I don't see you malloc() it anywhere. Right, free() is not needed. File payloads/libpayload/tests/libc/fmap_locate_area-test.c: https://review.coreboot.org/c/coreboot/+/59494/comment/2e6c51ff_34f59a1c PS7, Line 78: u8 fmap_buffer2[sizeof(struct fmap) + 3 * sizeof(struct fmap_area)]; > Is this still used? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Gerrit-Change-Number: 59494 Gerrit-PatchSet: 9 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Dec 2021 16:24:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add commonlib/bsd include path to lpgcc
by Jakub Czapiga (Code Review) 16 Dec '21

16 Dec '21

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60171 ) Change subject: libpayload: Add commonlib/bsd include path to lpgcc ...................................................................... libpayload: Add commonlib/bsd include path to lpgcc coreinfo and nvramcui are using libpayload/bin/lpgcc and libpayload build directory as a base, instead of installing it first. This caused include errors, because commonlib/bsd is not present there. This patch introduces comonlib/bsd include path to lpgcc CFLAGS if it is being built using libpayload build directory as a base. Change-Id: I7d1fe9e5dc3e7c1c1ba825a1bf19972722b42778 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M payloads/libpayload/bin/lpgcc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/60171/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 3a76f13..a0b736b 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -167,6 +167,8 @@ if [ "$CONFIG_LP_TINYCURSES" = y ]; then _CFLAGS="$_CFLAGS -I$BASE/../curses" fi + + _CFLAGS="$_CFLAGS -I$BASE/../../../src/commonlib/bsd/include" fi # Check for the -fno-stack-protector silliness -- To view, visit https://review.coreboot.org/c/coreboot/+/60171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d1fe9e5dc3e7c1c1ba825a1bf19972722b42778 Gerrit-Change-Number: 60171 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
by Saurabh Mishra (Code Review) 16 Dec '21

16 Dec '21

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60170 ) Change subject: Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> ...................................................................... Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers. change-Id: I0c6ae72610da39fc18ff252c440d006e83c570c1 --- M src/soc/intel/alderlake/meminit.c 1 file changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/60170/1 diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 44071db..d81e856 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -123,14 +123,14 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) { uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { - [0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, }, - [1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, }, - [2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, }, - [3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, }, - [4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, }, - [5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, }, - [6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, }, - [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, + [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [1] = { &mem_cfg->MemorySpdPtr002, &mem_cfg->MemorySpdPtr003, }, + [2] = { &mem_cfg->MemorySpdPtr004, &mem_cfg->MemorySpdPtr005, }, + [3] = { &mem_cfg->MemorySpdPtr006, &mem_cfg->MemorySpdPtr007, }, + [4] = { &mem_cfg->MemorySpdPtr008, &mem_cfg->MemorySpdPtr009, }, + [5] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, + [6] = { &mem_cfg->MemorySpdPtr012, &mem_cfg->MemorySpdPtr013, }, + [7] = { &mem_cfg->MemorySpdPtr014, &mem_cfg->MemorySpdPtr015, }, }; uint8_t *disable_channel_upds[MRC_CHANNELS] = { &mem_cfg->DisableMc0Ch0, @@ -179,17 +179,17 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dq_upds[MRC_CHANNELS] = { - &mem_cfg->DqMapCpu2DramCh0, - &mem_cfg->DqMapCpu2DramCh1, - &mem_cfg->DqMapCpu2DramCh2, - &mem_cfg->DqMapCpu2DramCh3, - &mem_cfg->DqMapCpu2DramCh4, - &mem_cfg->DqMapCpu2DramCh5, - &mem_cfg->DqMapCpu2DramCh6, - &mem_cfg->DqMapCpu2DramCh7, + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch1, + &mem_cfg->DqMapCpu2DramMc0Ch2, + &mem_cfg->DqMapCpu2DramMc0Ch3, + &mem_cfg->DqMapCpu2DramMc0Ch4, + &mem_cfg->DqMapCpu2DramMc0Ch5, + &mem_cfg->DqMapCpu2DramMc0Ch6, + &mem_cfg->DqMapCpu2DramMc0Ch7, }; - const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0); _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!"); @@ -200,17 +200,17 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dqs_upds[MRC_CHANNELS] = { - &mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1, - &mem_cfg->DqsMapCpu2DramCh2, - &mem_cfg->DqsMapCpu2DramCh3, - &mem_cfg->DqsMapCpu2DramCh4, - &mem_cfg->DqsMapCpu2DramCh5, - &mem_cfg->DqsMapCpu2DramCh6, - &mem_cfg->DqsMapCpu2DramCh7, + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch1, + &mem_cfg->DqsMapCpu2DramMc0Ch2, + &mem_cfg->DqsMapCpu2DramMc0Ch3, + &mem_cfg->DqsMapCpu2DramMc0Ch4, + &mem_cfg->DqsMapCpu2DramMc0Ch5, + &mem_cfg->DqsMapCpu2Drammc0Ch6, + &mem_cfg->DqsMapCpu2DramMc0Ch7, }; - const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0); _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!"); -- To view, visit https://review.coreboot.org/c/coreboot/+/60170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570c1 Gerrit-Change-Number: 60170 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: Add Board values for eDP tuning
by Raul Rangel (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Bao Zheng, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59919 ) Change subject: mb/google/guybrush/var/nipperkin: Add Board values for eDP tuning ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Gerrit-Change-Number: 59919 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 16 Dec 2021 15:41:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
by Raul Rangel (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Nico Huber, Marshall Dawson, Zheng Bao, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 ) Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning ...................................................................... Patch Set 6: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59918/comment/71649ab8_796a9149 PS5, Line 11: https://partnerissuetracker.corp.google.com/issues/203061533#comment6 > https://issuetracker.google.com/issues/203061533#comment6 would be the public link. […] Done Patchset: PS6: There is still one outstanding comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/59918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Gerrit-Change-Number: 59918 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 16 Dec 2021 15:41:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Implement new CBFS access API
by Jakub Czapiga (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Jakub Czapiga, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59497 to look at the new patch set (#9). Change subject: libpayload: Implement new CBFS access API ...................................................................... libpayload: Implement new CBFS access API Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile.inc M payloads/libpayload/include/cbfs.h A payloads/libpayload/include/cbfs_boot_device.h M payloads/libpayload/include/cbfs_core.h A payloads/libpayload/include/cbfs_glue.h A payloads/libpayload/include/cbfs_legacy.h A payloads/libpayload/libcbfs/Kconfig M payloads/libpayload/libcbfs/Makefile.inc M payloads/libpayload/libcbfs/cbfs.c M payloads/libpayload/libcbfs/cbfs_core.c A payloads/libpayload/libcbfs/cbfs_legacy.c M payloads/libpayload/tests/Makefile.inc A payloads/libpayload/tests/include/mocks/cbfs_util.h A payloads/libpayload/tests/libcbfs/Makefile.inc A payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c A payloads/libpayload/tests/libcbfs/cbfs-verification-test.c A payloads/libpayload/tests/mocks/cbfs_file_mock.c A payloads/libpayload/tests/mocks/die.c 19 files changed, 2,103 insertions(+), 431 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/59497/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7 Gerrit-Change-Number: 59497 Gerrit-PatchSet: 9 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Enable vboot integration
by Jakub Czapiga (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Jakub Czapiga, Jan Dabros, Yu-Ping Wu. Hello build bot (Jenkins), Julius Werner, Jan Dabros, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60080 to look at the new patch set (#4). Change subject: libpayload: Enable vboot integration ...................................................................... libpayload: Enable vboot integration This patch introduces building and linking of 3rdparty/vboot with libpayload. VBoot configuration can be set using CONFIG_LP_VBOOT and other entries from VBoot Kconfig menu. Change-Id: I2d9d766a461edaa0081041c020ecf580fd2ca64e Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/vboot/Kconfig A payloads/libpayload/vboot/Makefile.inc 5 files changed, 100 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/60080/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d9d766a461edaa0081041c020ecf580fd2ca64e Gerrit-Change-Number: 60080 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/libc/fmap: Implement new FlashMap API
by Jakub Czapiga (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Jakub Czapiga. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59494 to look at the new patch set (#8). Change subject: libpayload/libc/fmap: Implement new FlashMap API ...................................................................... libpayload/libc/fmap: Implement new FlashMap API This patch introduces new FlashMap API, the fmap_locate_area(). It works on cached FlashMap provided in lib_sysinfo.fmap_cache. Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- A payloads/libpayload/include/fmap.h D payloads/libpayload/include/fmap_serialized.h M payloads/libpayload/include/libpayload.h M payloads/libpayload/libc/fmap.c A payloads/libpayload/tests/libc/Makefile.inc A payloads/libpayload/tests/libc/fmap_locate_area-test.c 6 files changed, 180 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/59494/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb Gerrit-Change-Number: 59494 Gerrit-PatchSet: 8 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE
by Rob Barnes (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Paul Menzel, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60139 ) Change subject: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Ah, I forgot that coreboot needs this to compile when VBOOT_STARTS_BEFORE_BOOTBLOCK=n. -- To view, visit https://review.coreboot.org/c/coreboot/+/60139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Gerrit-Change-Number: 60139 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 16 Dec 2021 15:35:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021