coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
by Saurabh Mishra (Code Review) 16 Dec '21

16 Dec '21

Saurabh Mishra has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/60170 ) Change subject: Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/60170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570c1 Gerrit-Change-Number: 60170 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
by Saurabh Mishra (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Tim Wawrzynczak. Saurabh Mishra has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/60170 ) Change subject: Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/60170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570c1 Gerrit-Change-Number: 60170 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: libpayload/i8042: Use 'INFO' instead of 'ERROR' when probing failed
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Nico Huber, Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60129 ) Change subject: libpayload/i8042: Use 'INFO' instead of 'ERROR' when probing failed ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60129/comment/1f42b971_24732d66 PS2, Line 13: when doing the autotest. > The autotest scans the 'ERROR' log in the bios log. Sort of. Yes, one our testing tool scans the coreboot log for `ERROR:` to determine if there were any critical errors during boot. Perhaps this is a tad simplistic. But, does it have to be reported as a kind of critical error if the i/o port probe fails? Maybe WARNING would be more appropriate here? -- To view, visit https://review.coreboot.org/c/coreboot/+/60129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2880c854b873a2a00aa0d8b1cbb4f86fa8139255 Gerrit-Change-Number: 60129 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Dec 2021 16:46:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/brask: Disable autonomous GPIO power management
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Paul Menzel, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60100 ) Change subject: mb/google/brya/variants/brask: Disable autonomous GPIO power management ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5 Gerrit-Change-Number: 60100 Gerrit-PatchSet: 5 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Dec 2021 16:42:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "security/vboot: Add NVRAM counter for TPM 2.0"
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Miriam Polzer, Andrey Pronin, Tim Wawrzynczak, Julius Werner, Yu-Ping Wu. Hello Miriam Polzer, build bot (Jenkins), Andrey Pronin, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60030 to look at the new patch set (#2). Change subject: Revert "security/vboot: Add NVRAM counter for TPM 2.0" ...................................................................... Revert "security/vboot: Add NVRAM counter for TPM 2.0" This reverts commit 7dce19080889955576f8fd197658077aced96a96. Reason for revert: Unable to boot in factory mode Change-Id: I1b51010080164c6e28d77a932f77c10006fd4153 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/security/vboot/antirollback.h M src/security/vboot/secdata_tpm.c 2 files changed, 0 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/60030/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b51010080164c6e28d77a932f77c10006fd4153 Gerrit-Change-Number: 60030 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Miriam Polzer <mpolzer(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Miriam Polzer <mpolzer(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE
by Rob Barnes (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Paul Menzel, Karthik Ramasubramanian. Hello Raul Rangel, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60139 to look at the new patch set (#3). Change subject: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE ...................................................................... mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will cause verstage to run during s0i3 resume. The TPM will be reinitialized in verstage during s0i3 resume. This is necessary on guybrush boards because the TPM_RST_L pin is asserted by the SOC in S0i3. BUG=b:200578885 BRANCH=None TEST=TPM initialized after s0i3 Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/60139/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Gerrit-Change-Number: 60139 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/vboot: Add NVRAM counter for TPM 2.0
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Tim Wawrzynczak has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/59097 ) Change subject: security/vboot: Add NVRAM counter for TPM 2.0 ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/59097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I511dba3b3461713ce20fb2bda9fced0fee6517e1 Gerrit-Change-Number: 59097 Gerrit-PatchSet: 8 Gerrit-Owner: Miriam Polzer <mpolzer(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "security/vboot: Add NVRAM counter for TPM 2.0"
by Tim Wawrzynczak (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Miriam Polzer, Andrey Pronin, Julius Werner, Yu-Ping Wu. Hello Miriam Polzer, build bot (Jenkins), Andrey Pronin, Julius Werner, Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/60030 to review the following change. Change subject: Revert "security/vboot: Add NVRAM counter for TPM 2.0" ...................................................................... Revert "security/vboot: Add NVRAM counter for TPM 2.0" This reverts commit 7dce19080889955576f8fd197658077aced96a96. Reason for revert: Unable to boot in factory mode Change-Id: I1b51010080164c6e28d77a932f77c10006fd4153 --- M src/security/vboot/antirollback.h M src/security/vboot/secdata_tpm.c 2 files changed, 0 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/60030/1 diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 2297762..a208c04 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -28,7 +28,6 @@ /* 0x100d: Hash of MRC_CACHE training data for non-recovery boot */ #define MRC_RW_HASH_NV_INDEX 0x100d #define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE -#define ENT_ROLLBACK_COUNTER_INDEX 0x100e /* Zero-Touch Enrollment related spaces */ #define ZTE_BOARD_ID_NV_INDEX 0x3fff00 #define ZTE_RMA_SN_BITS_INDEX 0x3fff01 diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 47efe2d..0bc4f839 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -116,17 +116,6 @@ .TPMA_NV_WRITE_STCLEAR = 1, }; -const static TPMA_NV rw_counter_attributes = { - .TPMA_NV_AUTHWRITE = 1, - .TPMA_NV_AUTHREAD = 1, - .TPMA_NV_PPREAD = 1, - .TPMA_NV_PPWRITE = 1, - .TPMA_NV_PLATFORMCREATE = 1, - .TPMA_NV_COUNTER = 1, - .TPMA_NV_NO_DA = 1, - .TPMA_NV_WRITE_STCLEAR = 1, -}; - static const TPMA_NV fwmp_attr = { .TPMA_NV_PLATFORMCREATE = 1, .TPMA_NV_OWNERWRITE = 1, @@ -341,15 +330,6 @@ return rv; } -static uint32_t enterprise_rollback_create_counter(void) -{ - /* - * No need to increment the counter to initialize, this can be done later. - */ - return tlcl_define_space(ENT_ROLLBACK_COUNTER_INDEX, /*size=*/8, - rw_counter_attributes, NULL, 0); -} - static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { RETURN_ON_FAILURE(tlcl_force_clear()); @@ -383,14 +363,6 @@ CONFIG(MAINBOARD_HAS_I2C_TPM_CR50)))) RETURN_ON_FAILURE(setup_zte_spaces()); - /* - * On TPM 2.0, create a counter that survives TPM clear. This allows to - * securely lock data during enterprise rollback by binding to this - * counter's value. - */ - if (CONFIG(CHROMEOS)) - RETURN_ON_FAILURE(enterprise_rollback_create_counter()); - RETURN_ON_FAILURE(setup_firmware_space(ctx)); return TPM_SUCCESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/60030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b51010080164c6e28d77a932f77c10006fd4153 Gerrit-Change-Number: 60030 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Miriam Polzer <mpolzer(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Miriam Polzer <mpolzer(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Implement new CBFS access API
by Jakub Czapiga (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Paul Menzel, Julius Werner. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59497 ) Change subject: libpayload: Implement new CBFS access API ...................................................................... Patch Set 10: (4 comments) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/59497/comment/f20afe67_18e8cb33 PS8, Line 211: config CBFS > nit: maybe makes sense to just move this into libcbfs/Kconfig as well now? As you suggested in CB:60080, I moved VBOOT_LIB here. I think, that both should be in same place, as both enable building additional libraries. File payloads/libpayload/include/cbfs_core.h: https://review.coreboot.org/c/coreboot/+/59497/comment/086779f2_2a91b80b PS5, Line 87: #define CBFS_ATTRIBUTE_ALIGN 4 > You're still adding METADATA_MAX_SIZE and a _Static_assert() to cbfs_core. […] Ok, I think, that I removed all redefs. File payloads/libpayload/include/cbfs_glue.h: https://review.coreboot.org/c/coreboot/+/59497/comment/2eb943ab_7b3e391a PS3, Line 38: { > This, too, this is still open. (Also, I don't know how that second comment slipped in there... […] Thanks for explaining it. I didn't look at it that way. I believe, we had a problem with overflow checking before. GCC will optimize-out `offset + size < offset and replace as false, for signed types. If offset and size will be unsigned, there should be no problem. But, should not this code also perform checks including dev->offset? File payloads/libpayload/libcbfs/cbfs.c: https://review.coreboot.org/c/coreboot/+/59497/comment/27eb89ad_1ddd934c PS3, Line 60: void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, bool is_ro); > Sorry, I should have unresolved this, it kinda slipped through now. I marked it as static. Please take a look at current solution (in tests too). -- To view, visit https://review.coreboot.org/c/coreboot/+/59497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7 Gerrit-Change-Number: 59497 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Dec 2021 16:29:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Enable vboot integration
by Jakub Czapiga (Code Review) 16 Dec '21

16 Dec '21

Attention is currently required from: Julius Werner, Jan Dabros, Yu-Ping Wu. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60080 ) Change subject: libpayload: Enable vboot integration ...................................................................... Patch Set 5: (7 comments) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/60080/comment/7379807a_46c40870 PS3, Line 230: endmenu > Should we put vboot in this menu with the other libraries, maybe? Done File payloads/libpayload/Makefile.inc: https://review.coreboot.org/c/coreboot/+/60080/comment/019f0185_58a39ba2 PS2, Line 82: $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) > No, I'm saying there shouldn't be a vboot.a. There should only be vboot_fw.a and tlcl.a. […] I think, that vboot libraries should not be in libc-objs, because vboot can be enabled without libc. I split vboot_fw and tlcl to separate classes so vboot_fw.a and tlcl.a are now compiled. So, there is a question: do we want to install vboot_fw.a and tlcl.a? I'd say yes. File payloads/libpayload/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/60080/comment/4b71558a_3f7cce37 PS3, Line 5: config VBOOT > Actually, on second thought maybe it would be better to call this CONFIG_VBOOT_LIB and make the text […] Done https://review.coreboot.org/c/coreboot/+/60080/comment/0ab38ea2_c46b12c2 PS3, Line 13: config VBOOT_DEBUG > Forgot to take this out? Done https://review.coreboot.org/c/coreboot/+/60080/comment/d2df8ab0_6f614a45 PS3, Line 30: This option enables SHA256 implementation using x86 SHA processor extension. > Maybe list the instructions (sha256msg1, sha256msg2, sha256rnds2) like in the coreboot Kconfig, for […] Done File payloads/libpayload/vboot/Makefile.inc: https://review.coreboot.org/c/coreboot/+/60080/comment/6097049d_e0b012bb PS3, Line 18: VBOOT_CFLAGS += -I$(abspath $(obj)) -Wno-missing-prototypes > Are these two actually needed? I'm not sure what they're there for in coreboot, but it might be vest […] The second one is not required, vboot also uses -Wmissing-prototypes now. I copied it form the main coreboot vboot build target. `-I$(abspath $(obj))` is required to provide libpayload-config.h, which is included by include/kconfig.h. all includes are in libpayload CFLAGS, so we have to satisfy all of their requirements. https://review.coreboot.org/c/coreboot/+/60080/comment/7dadc27d_fa8e0c26 PS3, Line 23: VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 > Would be good to add an […] I intentionally left it without any check, because I wanted to allow building vboot for ARCH_MOCK. Now I added this assertion allowing but allowing it to be empty if we are compiling libpayload for ARCH_MOCK. (depthcharge unit-tests compile vboot witch FIRMWARE_ARCH=<empty>) -- To view, visit https://review.coreboot.org/c/coreboot/+/60080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d9d766a461edaa0081041c020ecf580fd2ca64e Gerrit-Change-Number: 60080 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 16 Dec 2021 16:28:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit December 2021