coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: libpayload/tests: Add libcbfs/cbfs_core-test test case
by Jakub Czapiga (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Paul Fagerburg, Julius Werner, Jan Dabros. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58327 ) Change subject: libpayload/tests: Add libcbfs/cbfs_core-test test case ...................................................................... Patch Set 2: (1 comment) This change is ready for review. Patchset: PS2: Hi, I created this test to get familiar with libpayload/libcbfs. It has 94.7% of coverage. Remaining 5.3% is cbfs_get_file_content(). Right now I will be working on porting coreboot implementation to libpayload, and this test will be a base to provide compatibility for payloads using older API. -- To view, visit https://review.coreboot.org/c/coreboot/+/58327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib246a891242f5a514f2f142699800eeb407de4f9 Gerrit-Change-Number: 58327 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 17:03:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [RFC] soc/amd/*/cpu: handle mp_init_with_smm failure
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58859 ) Change subject: [RFC] soc/amd/*/cpu: handle mp_init_with_smm failure ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/cpu.c: https://review.coreboot.org/c/coreboot/+/58859/comment/bb2c7ad3_5fa824fb PS1, Line 55: die Can you die with a post code? -- To view, visit https://review.coreboot.org/c/coreboot/+/58859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Gerrit-Change-Number: 58859 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 16:43:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [RFC] soc/amd/*/cpu: handle mp_init_with_smm failure
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58859 ) Change subject: [RFC] soc/amd/*/cpu: handle mp_init_with_smm failure ...................................................................... [RFC] soc/amd/*/cpu: handle mp_init_with_smm failure When the mp_init_with_smm call returns a failure, coreboot can't just continue with the initialization and boot process due to the system being in a bad state. Ignoring the failure here will just cause the boot process failing elsewhere where it may not be obvious that the failed multi-processor initialization step was the root cause of that. I'm not 100% sure if calling do_cold_reset or calling die is the better option here. Calling do_cold_reset likely here would likely result in a boot-failure loop, so I call die here. BUG=b:193809448 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/stoneyridge/cpu.c 3 files changed, 6 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/58859/1 diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index c3d89bf..103ece0 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -51,9 +51,8 @@ void mp_init_cpus(struct bus *cpu_bus) { - /* Clear for take-off */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die("mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 9822326..f1f5897 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -55,9 +55,8 @@ void mp_init_cpus(struct bus *cpu_bus) { - /* Clear for take-off */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die("mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 0655032..5297ee7 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -52,9 +52,8 @@ void mp_init_cpus(struct bus *cpu_bus) { - /* Clear for take-off */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die("mp_init_with_smm failed. Halting.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); -- To view, visit https://review.coreboot.org/c/coreboot/+/58859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Gerrit-Change-Number: 58859 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/stoneyridge/cpu: remove unneeded line break in get_cpu_count
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58858 ) Change subject: soc/amd/stoneyridge/cpu: remove unneeded line break in get_cpu_count ...................................................................... soc/amd/stoneyridge/cpu: remove unneeded line break in get_cpu_count The line length is no longer limited to 80 characters, so there's no need for that line break any more. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7a8fb472f00e039f25a71ee526a3dd0bc6c754f6 --- M src/soc/amd/stoneyridge/cpu.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/58858/1 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 99b40a6..0655032 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -39,8 +39,7 @@ static int get_cpu_count(void) { - return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) - + 1; + return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1; } static const struct mp_ops mp_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/58858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a8fb472f00e039f25a71ee526a3dd0bc6c754f6 Gerrit-Change-Number: 58858 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/amd: Always fetch cpu addr bits at runtime
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58686 ) Change subject: cpu/amd: Always fetch cpu addr bits at runtime ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: would be good if you can address the remaining open comments on the commit message so that it can be submitted -- To view, visit https://review.coreboot.org/c/coreboot/+/58686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e Gerrit-Change-Number: 58686 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 02 Nov 2021 16:04:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/trogdor: Mark kingoftown as supporting Parade PS84640
by Philip Chen (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Kevin Chiu, Douglas Anderson, Paul Menzel. Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58789 ) Change subject: mb/google/trogdor: Mark kingoftown as supporting Parade PS84640 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie13ddfef6adfd53adb0a0d3a98995fb00b8a45e6 Gerrit-Change-Number: 58789 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Douglas Anderson <dianders(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 16:03:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Fetch addr bits at runtime
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58687 ) Change subject: soc/intel/denverton_ns: Fetch addr bits at runtime ...................................................................... soc/intel/denverton_ns: Fetch addr bits at runtime Change-Id: Ic46a7d56cbaf45724ebc2a1911f5096af2fe461a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58687 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/acpi.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Mariusz Szafrański: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 82b8cf1..ab6e7cc 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -4,6 +4,7 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> +#include <cpu/cpu.h> #include <cpu/x86/smm.h> #include <string.h> #include <device/pci.h> @@ -60,7 +61,7 @@ gnvs->mmiob = (u32)get_top_of_low_memory(); gnvs->mmiol = (u32)(get_pciebase() - 1); gnvs->mmiohb = (u64)get_top_of_upper_memory(); - gnvs->mmiohl = (u64)(((u64)1 << CONFIG_CPU_ADDR_BITS) - 1); + gnvs->mmiohl = (u64)(((u64)1 << cpu_phys_address_size()) - 1); gnvs->tsegb = (u32)get_tseg_memory(); gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory()); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic46a7d56cbaf45724ebc2a1911f5096af2fe461a Gerrit-Change-Number: 58687 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Revert "mb/google/brya/var/kano: disabled autonomous GPIO power manag...
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58809 ) Change subject: Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management" ...................................................................... Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management" This reverts commit 287cc02c007fd47b515d19389ea00ea0461fd5a1. Reason for revert: it will break s0ix. BUG=b:201266532 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 0 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index e650042..899dd36 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -15,17 +15,6 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - # This disabled autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada Gerrit-Change-Number: 58809 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in edk2[coreboot-stable202108]: UefiPayloadPkg: Add build option to disable Above 4G Decode
by Sean Rhodes (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/edk2/+/58801 ) Change subject: UefiPayloadPkg: Add build option to disable Above 4G Decode ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/edk2/+/58801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I50e9d9052b344519f46419a01b27b2ca43047943 Gerrit-Change-Number: 58801 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 15:57:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in edk2[coreboot-stable202108]: UefiPayloadPkg: Add build option to disable Above 4G Decode
by Matt DeVillier (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/edk2/+/58801 ) Change subject: UefiPayloadPkg: Add build option to disable Above 4G Decode ...................................................................... Patch Set 4: (1 comment) File UefiPayloadPkg/UefiPayloadPkg.dsc: https://review.coreboot.org/c/edk2/+/58801/comment/9c951c39_7916409d PS1, Line 327: DECODE > that's what I get for pulling it directly from your repo and not mine =P Done -- To view, visit https://review.coreboot.org/c/edk2/+/58801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I50e9d9052b344519f46419a01b27b2ca43047943 Gerrit-Change-Number: 58801 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Tue, 02 Nov 2021 15:57:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021