coreboot-gerrit November 2021

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Change in coreboot[master]: include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58696 ) Change subject: include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs ...................................................................... include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in the code where the defines are used to clarify which ID is used on which hardware generation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/smbus/sm.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/sm.c 5 files changed, 6 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 0e4da41..1ed6ac9 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -620,8 +620,6 @@ #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1 0x7917 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD 0x7906 -#define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B -#define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE 0x1641 #define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97 0x1644 diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 496816b..7c46645 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -322,9 +322,10 @@ }; static const unsigned short pci_device_ids[] = { + /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */ PCI_DEVICE_ID_AMD_SB900_LPC, + /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */ PCI_DEVICE_ID_AMD_CZ_LPC, - PCI_DEVICE_ID_AMD_FAM17H_LPC, 0 }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index ce66cbb..ae2edc1 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -89,5 +89,6 @@ static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_AMD, + /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */ .device = PCI_DEVICE_ID_AMD_CZ_SMBUS, }; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 77d39c5..784147c 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -354,7 +354,9 @@ }; static const unsigned short pci_device_ids[] = { + /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */ PCI_DEVICE_ID_AMD_SB900_LPC, + /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */ PCI_DEVICE_ID_AMD_CZ_LPC, 0 }; diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 6f9e03c..f6422cf 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -106,5 +106,6 @@ static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_AMD, + /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */ .device = PCI_DEVICE_ID_AMD_SB900_SM, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/58696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Gerrit-Change-Number: 58696 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in edk2[coreboot-stable202108]: UefiPayloadPkg: Add build option to disable Above 4G Decode
by Matt DeVillier (Code Review) 02 Nov '21

02 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/edk2/+/58801 to look at the new patch set (#4). Change subject: UefiPayloadPkg: Add build option to disable Above 4G Decode ...................................................................... UefiPayloadPkg: Add build option to disable Above 4G Decode Add build option `ABOVE_4G_MEMORY`, which when disabled, will dispatch everything under 4GB. This allows OSes that require EFI_LOADED_IMAGE to be under 4GB to start (e.g. Xen hypervisor used in Qubes OS). Dovetails with coreboot commit 766e481a: "payloads/external/tianocore: Add build argument for 4G Decode" Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I50e9d9052b344519f46419a01b27b2ca43047943 --- M UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c M UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf M UefiPayloadPkg/UefiPayloadPkg.dec M UefiPayloadPkg/UefiPayloadPkg.dsc 4 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/edk2 refs/changes/01/58801/4 -- To view, visit https://review.coreboot.org/c/edk2/+/58801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I50e9d9052b344519f46419a01b27b2ca43047943 Gerrit-Change-Number: 58801 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

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Change in edk2[master]: UefiPayloadPkg: Allow below 4GB memory
by Sean Rhodes (Code Review) 02 Nov '21

02 Nov '21

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/edk2/+/58802 ) Change subject: UefiPayloadPkg: Allow below 4GB memory ...................................................................... Abandoned Wrong branch -- To view, visit https://review.coreboot.org/c/edk2/+/58802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: master Gerrit-Change-Id: Ic600e08c9d46d0a291b8b119a3c268e432267cdf Gerrit-Change-Number: 58802 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: abandon

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Change in edk2[coreboot-stable202108]: UefiPayloadPkg: Add build option to disable Above 4G Decode
by Matt DeVillier (Code Review) 02 Nov '21

02 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/edk2/+/58801 to look at the new patch set (#3). Change subject: UefiPayloadPkg: Add build option to disable Above 4G Decode ...................................................................... UefiPayloadPkg: Add build option to disable Above 4G Decode Add build option `ABOVE_4G_MEMORY`, which when disabled, will dispatch everything under 4GB. This allows Operating System's that require EFI_LOADED_IMAGE to be under 4GB to start. e.g. Xen hypervisor used in Qubes Dovetails with coreboot commit 766e481a: "payloads/external/tianocore: Add build argument for 4G Decode" Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I50e9d9052b344519f46419a01b27b2ca43047943 --- M UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c M UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf M UefiPayloadPkg/UefiPayloadPkg.dec M UefiPayloadPkg/UefiPayloadPkg.dsc 4 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/edk2 refs/changes/01/58801/3 -- To view, visit https://review.coreboot.org/c/edk2/+/58801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I50e9d9052b344519f46419a01b27b2ca43047943 Gerrit-Change-Number: 58801 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

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Change in edk2[coreboot-stable202108]: UefiPayloadPkg: Add build option to disable Above 4G Decode
by Matt DeVillier (Code Review) 02 Nov '21

02 Nov '21

Matt DeVillier has restored this change. ( https://review.coreboot.org/c/edk2/+/58801 ) Change subject: UefiPayloadPkg: Add build option to disable Above 4G Decode ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/edk2/+/58801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I50e9d9052b344519f46419a01b27b2ca43047943 Gerrit-Change-Number: 58801 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: restore

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Change in coreboot[master]: include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58696 ) Change subject: include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Gerrit-Change-Number: 58696 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 15:40:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED]soc/intel/common/block/power_limit: Compute pl1_time msr value
by Arthur Heymans (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58857 to look at the new patch set (#2). Change subject: [UNTESTED]soc/intel/common/block/power_limit: Compute pl1_time msr value ...................................................................... [UNTESTED]soc/intel/common/block/power_limit: Compute pl1_time msr value Instead of using a static lookup table compute the best value at runtime. This also removes the 128s limit. Change-Id: I3a66b86b61e512a45daaa06d2c459a200413ecdf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 2 files changed, 41 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/58857/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a66b86b61e512a45daaa06d2c459a200413ecdf Gerrit-Change-Number: 58857 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [UNTESTED]soc/intel/common/block/power_limit: Compute pl1_time msr value
by build bot (Jenkins) (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58857 ) Change subject: [UNTESTED]soc/intel/common/block/power_limit: Compute pl1_time msr value ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/power_limit/power_limit.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132043): https://review.coreboot.org/c/coreboot/+/58857/comment/524d895f_ddb0dc3c PS1, Line 81: > ABS(power_limit_1_time - power_limit_time(time_unit_bits, y, z))) { line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/58857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a66b86b61e512a45daaa06d2c459a200413ecdf Gerrit-Change-Number: 58857 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 15:24:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED]soc/intel/common/block/power_limit: Compute pl1_time msr value
by Arthur Heymans (Code Review) 02 Nov '21

02 Nov '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58857 ) Change subject: [UNTESTED]soc/intel/common/block/power_limit: Compute pl1_time msr value ...................................................................... [UNTESTED]soc/intel/common/block/power_limit: Compute pl1_time msr value Instead of using a static lookup table compute the best value at runtime. This also removes the 128s limit. Change-Id: I3a66b86b61e512a45daaa06d2c459a200413ecdf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 2 files changed, 38 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/58857/1 diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index 3f18126..93b22b8 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -37,7 +37,7 @@ }; /* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time, +void set_power_limits(int power_limit_1_time, struct soc_power_limits_config *config); u8 get_cpu_tdp(void); diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index 417dd04..2b71e0e 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -7,69 +7,19 @@ #include <soc/msr.h> #include <soc/systemagent.h> -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; +/* Returns time limit in s depending on Y, Z and TU */ +static int power_limit_time(uint8_t tu_bits, uint8_t y, uint8_t z) +{ + if (y < tu_bits) + return 0; + return POWER_OF_2(y - tu_bits) * (4 + z) / 4; +} /* * Configure processor power limits if possible * This must be done AFTER set of BIOS_RESET_CPL */ -void set_power_limits(u8 power_limit_1_time, +void set_power_limits(int power_limit_1_time, struct soc_power_limits_config *conf) { msr_t msr = rdmsr(MSR_PLATFORM_INFO); @@ -78,10 +28,6 @@ unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = - ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; @@ -98,17 +44,12 @@ printk(BIOS_INFO, "CPU TDP = %u Watts\n", tdp / power_unit); - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - if (min_power > 0 && tdp < min_power) tdp = min_power; if (max_power > 0 && tdp > max_power) tdp = max_power; - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - /* Set long term power limit to TDP */ limit.lo = 0; tdp_pl1 = ((conf->tdp_pl1_override == 0) ? @@ -119,6 +60,35 @@ /* Set PL1 Pkg Power clamp bit */ limit.lo |= PKG_POWER_LIMIT_CLAMP; + /* + * RAPL time window calculation defined as follows: + * Time Window = Time_Unit * (1+X/4)*(2*^Y), X Corresponds to [23:22], + * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. + */ + { +#define MSR_RAPL_POWER_UNIT 0x606 + + /* bits 16:19 = 2 ^ - time_unit */ + const uint8_t time_unit_bits = (rdmsr(MSR_RAPL_POWER_UNIT).lo >> 16) & 0xf; + /* Start at 1s */ + uint8_t best_y = time_unit_bits; + uint8_t best_z = 0; + int closest_time = power_limit_time(time_unit_bits, best_y, best_z); + + for (uint8_t y = time_unit_bits; y <= 0x1f; y++) { + for (uint8_t z = 0; z < 4; z++) { + if (ABS(power_limit_1_time - closest_time) + > ABS(power_limit_1_time - power_limit_time(time_unit_bits, y, z))) { + closest_time = power_limit_time(time_unit_bits, y, z); + best_y = y; + best_z = z; + } + } + } + + power_limit_1_val = (best_y & 0x1f) | ((best_z & 3) << 5); + } + limit.lo |= PKG_POWER_LIMIT_EN; limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; -- To view, visit https://review.coreboot.org/c/coreboot/+/58857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a66b86b61e512a45daaa06d2c459a200413ecdf Gerrit-Change-Number: 58857 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] util: Add GUI to change CMOS settings
by Sean Rhodes (Code Review) 02 Nov '21

02 Nov '21

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58854 ) Change subject: [WIP] util: Add GUI to change CMOS settings ...................................................................... Patch Set 11: (1 comment) This change is ready for review. File util/coreboot-configurator/src/application/coreboot_configurator.h: https://review.coreboot.org/c/coreboot/+/58854/comment/4edeb53c_83c6936d PS11, Line 69: void closeEvent(QCloseEvent * ev); > "foo * bar" should be "foo *bar" Jenkins, you are impossible to please. -- To view, visit https://review.coreboot.org/c/coreboot/+/58854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie654f6aca57a792be0c295afc081a95ed4d875d1 Gerrit-Change-Number: 58854 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 15:02:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021