coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/lib: Support fallback option for fw_config
by Subrata Banik (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Julius Werner, Nick Vaccaro, Raj Astekar, Srinidhi N Kaushik. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58833 ) Change subject: src/lib: Support fallback option for fw_config ...................................................................... Patch Set 4: (2 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/58833/comment/a6bed50d_9dbdd6c2 PS4, Line 408: FW_CONFIG_SOURCE_CBFS why can't FW_CONFIG_SOURCE_CBFS Kconfig exist in line 398 above ? https://review.coreboot.org/c/coreboot/+/58833/comment/6f77b591_67b927b8 PS4, Line 416: and remove one "and"? why not append this at line 406 itself ? -- To view, visit https://review.coreboot.org/c/coreboot/+/58833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff Gerrit-Change-Number: 58833 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 18:47:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58864 ) Change subject: soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7 Gerrit-Change-Number: 58864 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 18:37:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/include/aoac_defs: drop leading newline
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58863 ) Change subject: soc/amd/cezanne/include/aoac_defs: drop leading newline ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc Gerrit-Change-Number: 58863 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 18:37:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58862 ) Change subject: soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9 Gerrit-Change-Number: 58862 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 18:37:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58864 ) Change subject: soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard ...................................................................... soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard This makes this header file consistent with the rest. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7 --- M src/soc/amd/cezanne/include/soc/cppc.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/58864/1 diff --git a/src/soc/amd/cezanne/include/soc/cppc.h b/src/soc/amd/cezanne/include/soc/cppc.h index e2f4daa..cb2ffaf 100644 --- a/src/soc/amd/cezanne/include/soc/cppc.h +++ b/src/soc/amd/cezanne/include/soc/cppc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _CPU_AMD_COMMON_H -#define _CPU_AMD_COMMON_H +#ifndef AMD_CEZANNE_CPPC_H +#define AMD_CEZANNE_CPPC_H #include <types.h> #include <acpi/acpigen.h> @@ -10,4 +10,4 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version); void generate_cppc_entries(unsigned int core_id); -#endif +#endif # AMD_CEZANNE_CPPC_H -- To view, visit https://review.coreboot.org/c/coreboot/+/58864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7 Gerrit-Change-Number: 58864 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/include/aoac_defs: drop leading newline
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58863 ) Change subject: soc/amd/cezanne/include/aoac_defs: drop leading newline ...................................................................... soc/amd/cezanne/include/aoac_defs: drop leading newline Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc --- M src/soc/amd/cezanne/include/soc/aoac_defs.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/58863/1 diff --git a/src/soc/amd/cezanne/include/soc/aoac_defs.h b/src/soc/amd/cezanne/include/soc/aoac_defs.h index 5309cb0..25311dd 100644 --- a/src/soc/amd/cezanne/include/soc/aoac_defs.h +++ b/src/soc/amd/cezanne/include/soc/aoac_defs.h @@ -1,4 +1,3 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ #ifndef AMD_CEZANNE_AOAC_DEFS_H -- To view, visit https://review.coreboot.org/c/coreboot/+/58863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc Gerrit-Change-Number: 58863 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58862 ) Change subject: soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards ...................................................................... soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards Somehow missed renaming those when creating the coreboot support for Cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9 --- M src/soc/amd/cezanne/include/soc/platform_descriptors.h M src/soc/amd/cezanne/include/soc/uart.h 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/58862/1 diff --git a/src/soc/amd/cezanne/include/soc/platform_descriptors.h b/src/soc/amd/cezanne/include/soc/platform_descriptors.h index 3a4bc62..d6d65f0 100644 --- a/src/soc/amd/cezanne/include/soc/platform_descriptors.h +++ b/src/soc/amd/cezanne/include/soc/platform_descriptors.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H -#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H +#ifndef AMD_CEZANNE_PLATFORM_DESCRIPTORS_H +#define AMD_CEZANNE_PLATFORM_DESCRIPTORS_H #include <types.h> #include <platform_descriptors.h> @@ -14,4 +14,4 @@ void mb_pre_fspm(void); -#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */ +#endif /* AMD_CEZANNE_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/cezanne/include/soc/uart.h b/src/soc/amd/cezanne/include/soc/uart.h index 9b99cd4..8affe10 100644 --- a/src/soc/amd/cezanne/include/soc/uart.h +++ b/src/soc/amd/cezanne/include/soc/uart.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef AMD_PICASSO_UART_H -#define AMD_PICASSO_UART_H +#ifndef AMD_CEZANNE_UART_H +#define AMD_CEZANNE_UART_H #include <types.h> void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ -#endif /* AMD_PICASSO_UART_H */ +#endif /* AMD_CEZANNE_UART_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9 Gerrit-Change-Number: 58862 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Start preloading VGA_BIOS_FILE
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56582 to look at the new patch set (#6). Change subject: soc/amd/cezanne: Start preloading VGA_BIOS_FILE ...................................................................... soc/amd/cezanne: Start preloading VGA_BIOS_FILE This CL enables support for CBFS_PRELOAD and starts preloading the VGA_BIOS_FILE. The CBFS_SIZE was chosen because I will preload ramstage in follow up CLs and wanted it large enough to hold it. BUG=b:179699789 TEST=Boot guybrush to OS and see 12 ms reduction in boot time. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idc96299ee0186470df0ff113ecacb604a877f6ad --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/fsp_s_params.c 2 files changed, 16 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/56582/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc96299ee0186470df0ff113ecacb604a877f6ad Gerrit-Change-Number: 56582 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Add dep for COOP_MULTITASKING and PAYLOAD_PRELOAD
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58861 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Add dep for COOP_MULTITASKING and PAYLOAD_PRELOAD ...................................................................... soc/amd/cezanne: Add dep for COOP_MULTITASKING and PAYLOAD_PRELOAD This makes it easy to disable preloading by unselecting SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371 --- M src/soc/amd/cezanne/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/58861/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371 Gerrit-Change-Number: 58861 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Add dependency for COOP_MULTITASKING and PAYLOAD_PRE...
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58861 ) Change subject: soc/amd/cezanne: Add dependency for COOP_MULTITASKING and PAYLOAD_PRELOAD ...................................................................... soc/amd/cezanne: Add dependency for COOP_MULTITASKING and PAYLOAD_PRELOAD This makes it easy to disable preloading by unselecting SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371 --- M src/soc/amd/cezanne/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/58861/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index b9b7c70..63d9e13 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -19,7 +19,7 @@ select CPU_INFO_V2 select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE - select COOP_MULTITASKING + select COOP_MULTITASKING if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA @@ -31,7 +31,7 @@ select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select PARALLEL_MP_AP_WORK - select PAYLOAD_PRELOAD + select PAYLOAD_PRELOAD if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/58861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371 Gerrit-Change-Number: 58861 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021