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Change in coreboot[master]: mb/system76/gaze15: Convert to variant setup
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58675 ) Change subject: mb/system76/gaze15: Convert to variant setup ...................................................................... mb/system76/gaze15: Convert to variant setup Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58675 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/system76/gaze15/Kconfig M src/mainboard/system76/gaze15/Makefile.inc M src/mainboard/system76/gaze15/board_info.txt M src/mainboard/system76/gaze15/bootblock.c M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/gaze15/dsdt.asl D src/mainboard/system76/gaze15/include/mainboard/gpio.h A src/mainboard/system76/gaze15/include/variant/gpio.h M src/mainboard/system76/gaze15/ramstage.c A src/mainboard/system76/gaze15/variants/gaze15/board_info.txt R src/mainboard/system76/gaze15/variants/gaze15/data.vbt R src/mainboard/system76/gaze15/variants/gaze15/gpio.c R src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c R src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c A src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb 15 files changed, 68 insertions(+), 65 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig index e6265e4..e82a845 100644 --- a/src/mainboard/system76/gaze15/Kconfig +++ b/src/mainboard/system76/gaze15/Kconfig @@ -17,7 +17,7 @@ select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO select SOC_INTEL_CANNONLAKE_PCH_H - select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMETLAKE_1 if BOARD_SYSTEM76_GAZE15 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP @@ -25,45 +25,43 @@ config MAINBOARD_DIR default "system76/gaze15" +config VARIANT_DIR + default "gaze15" if BOARD_SYSTEM76_GAZE15 + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER - default "gaze15" + default "gaze15" if BOARD_SYSTEM76_GAZE15 config MAINBOARD_SMBIOS_PRODUCT_NAME - string default "Gazelle" config MAINBOARD_VERSION - string - default "gaze15" + default "gaze15" if BOARD_SYSTEM76_GAZE15 config CBFS_SIZE default 0xA00000 config CONSOLE_POST - bool default y config ONBOARD_VGA_IS_PRIMARY - bool default y config UART_FOR_CONSOLE - int default 2 config MAX_CPUS - int default 16 config DIMM_MAX default 2 config VGA_BIOS_ID - string default "8086,9bc4" config POST_DEVICE - bool default n endif diff --git a/src/mainboard/system76/gaze15/Makefile.inc b/src/mainboard/system76/gaze15/Makefile.inc index 83ef3a5..32a4099 100644 --- a/src/mainboard/system76/gaze15/Makefile.inc +++ b/src/mainboard/system76/gaze15/Makefile.inc @@ -1,8 +1,10 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include bootblock-y += bootblock.c -bootblock-y += gpio_early.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += romstage.c ramstage-y += ramstage.c -ramstage-y += gpio.c -ramstage-y += hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/gaze15/board_info.txt b/src/mainboard/system76/gaze15/board_info.txt index 07130b5..badfb66 100644 --- a/src/mainboard/system76/gaze15/board_info.txt +++ b/src/mainboard/system76/gaze15/board_info.txt @@ -1,7 +1,5 @@ Vendor name: System76 -Board name: gaze15 Category: laptop -Release year: 2020 ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/system76/gaze15/bootblock.c b/src/mainboard/system76/gaze15/bootblock.c index ae416b4..b351fbd 100644 --- a/src/mainboard/system76/gaze15/bootblock.c +++ b/src/mainboard/system76/gaze15/bootblock.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <gpio.h> -#include <mainboard/gpio.h> +#include <variant/gpio.h> void bootblock_mainboard_early_init(void) { - mainboard_configure_early_gpios(); + variant_configure_early_gpios(); } diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index f8e879d..cf0965b 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -22,14 +22,6 @@ register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus - [PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console - }" - - # Misc register "AcousticNoiseMitigation" = "1" @@ -60,7 +52,6 @@ end device domain 0 on - subsystemid 0x1558 0x8520 inherit device pci 00.0 on end # Host Bridge device pci 01.0 on # GPU Port # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) @@ -101,24 +92,6 @@ end end device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 @@ -192,7 +165,7 @@ device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Interface + device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x00040069" register "gen2_dec" = "0x00fc0e01" register "gen3_dec" = "0x00fc0f01" diff --git a/src/mainboard/system76/gaze15/dsdt.asl b/src/mainboard/system76/gaze15/dsdt.asl index 8a3b4d7..d2bd57d 100644 --- a/src/mainboard/system76/gaze15/dsdt.asl +++ b/src/mainboard/system76/gaze15/dsdt.asl @@ -7,7 +7,7 @@ ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 /* OEM revision */ + 0x20110725 ) { #include <acpi/dsdt_top.asl> diff --git a/src/mainboard/system76/gaze15/include/mainboard/gpio.h b/src/mainboard/system76/gaze15/include/mainboard/gpio.h deleted file mode 100644 index c6393be..0000000 --- a/src/mainboard/system76/gaze15/include/mainboard/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -void mainboard_configure_early_gpios(void); -void mainboard_configure_gpios(void); - -#endif diff --git a/src/mainboard/system76/gaze15/include/variant/gpio.h b/src/mainboard/system76/gaze15/include/variant/gpio.h new file mode 100644 index 0000000..95d5762 --- /dev/null +++ b/src/mainboard/system76/gaze15/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/gaze15/ramstage.c b/src/mainboard/system76/gaze15/ramstage.c index ae2d741..ca6f64b1 100644 --- a/src/mainboard/system76/gaze15/ramstage.c +++ b/src/mainboard/system76/gaze15/ramstage.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <mainboard/gpio.h> #include <device/device.h> +#include <variant/gpio.h> -static void init_mainboard(void *chip_info) +static void mainboard_init(void *chip_info) { - mainboard_configure_gpios(); + variant_configure_gpios(); } struct chip_operations mainboard_ops = { - .init = init_mainboard, + .init = mainboard_init, }; diff --git a/src/mainboard/system76/gaze15/variants/gaze15/board_info.txt b/src/mainboard/system76/gaze15/variants/gaze15/board_info.txt new file mode 100644 index 0000000..a574325 --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze15/board_info.txt @@ -0,0 +1,2 @@ +Board name: gaze15 +Release year: 2020 diff --git a/src/mainboard/system76/gaze15/data.vbt b/src/mainboard/system76/gaze15/variants/gaze15/data.vbt similarity index 100% rename from src/mainboard/system76/gaze15/data.vbt rename to src/mainboard/system76/gaze15/variants/gaze15/data.vbt Binary files differ diff --git a/src/mainboard/system76/gaze15/gpio.c b/src/mainboard/system76/gaze15/variants/gaze15/gpio.c similarity index 99% rename from src/mainboard/system76/gaze15/gpio.c rename to src/mainboard/system76/gaze15/variants/gaze15/gpio.c index a9e6bb9..b7ae347 100644 --- a/src/mainboard/system76/gaze15/gpio.c +++ b/src/mainboard/system76/gaze15/variants/gaze15/gpio.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <mainboard/gpio.h> #include <soc/gpe.h> #include <soc/gpio.h> +#include <variant/gpio.h> static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPD ------- */ @@ -271,7 +271,7 @@ PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT# }; -void mainboard_configure_gpios(void) +void variant_configure_gpios(void) { gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } diff --git a/src/mainboard/system76/gaze15/gpio_early.c b/src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c similarity index 86% rename from src/mainboard/system76/gaze15/gpio_early.c rename to src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c index 881af89..38b1bc4 100644 --- a/src/mainboard/system76/gaze15/gpio_early.c +++ b/src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <mainboard/gpio.h> #include <soc/gpio.h> +#include <variant/gpio.h> static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD @@ -11,7 +11,7 @@ PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN }; -void mainboard_configure_early_gpios(void) +void variant_configure_early_gpios(void) { gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } diff --git a/src/mainboard/system76/gaze15/hda_verb.c b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c similarity index 100% rename from src/mainboard/system76/gaze15/hda_verb.c rename to src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c diff --git a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb new file mode 100644 index 0000000..1185223 --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb @@ -0,0 +1,31 @@ +chip soc/intel/cannonlake + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus + [PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console + }" + + device domain 0 on + subsystemid 0x1558 0x8520 inherit + + device pci 15.0 on # I2C0 + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/58675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123 Gerrit-Change-Number: 58675 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/gaze15: Convert to variant setup
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58675 ) Change subject: mb/system76/gaze15: Convert to variant setup ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123 Gerrit-Change-Number: 58675 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 19:22:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/oryp6: Add Oryx Pro 7 as a variant
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52296 ) Change subject: mb/system76/oryp6: Add Oryx Pro 7 as a variant ...................................................................... mb/system76/oryp6: Add Oryx Pro 7 as a variant Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52296 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/oryp7.md M src/mainboard/system76/oryp6/Kconfig M src/mainboard/system76/oryp6/Kconfig.name M src/mainboard/system76/oryp6/Makefile.inc A src/mainboard/system76/oryp6/include/variant/romstage.h M src/mainboard/system76/oryp6/romstage.c A src/mainboard/system76/oryp6/variants/oryp6/romstage.c A src/mainboard/system76/oryp6/variants/oryp7/board_info.txt A src/mainboard/system76/oryp6/variants/oryp7/data.vbt A src/mainboard/system76/oryp6/variants/oryp7/gpio.c A src/mainboard/system76/oryp6/variants/oryp7/gpio_early.c A src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c A src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb A src/mainboard/system76/oryp6/variants/oryp7/romstage.c 15 files changed, 437 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 908a163..28c500a 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -191,6 +191,7 @@ - [Lemur Pro 10](system76/lemp10.md) - [Oryx Pro 5](system76/oryp5.md) - [Oryx Pro 6](system76/oryp6.md) +- [Oryx Pro 7](system76/oryp7.md) ## Texas Instruments diff --git a/Documentation/mainboard/system76/oryp7.md b/Documentation/mainboard/system76/oryp7.md new file mode 100644 index 0000000..4672d67 --- /dev/null +++ b/Documentation/mainboard/system76/oryp7.md @@ -0,0 +1,71 @@ +# System76 Oryx Pro 7 (oryp7) + +## Specs + +- CPU + - Intel Core i7-10870H +- Chipset + - Intel HM470 +- EC + - ITE IT5570E running [System76 EC](https://github.com/system76/ec) +- Graphics + - dGPU options + - NVIDIA GeForce RTX 3060 + - NVIDIA GeForce RTX 3070 (Max-Q) + - NVIDIA GeForce RTX 3080 (Max-Q) + - eDP display options + - 15.6" 1920x1080@144Hz LCD (LG LP156WFG-SPB3) + - 15.6" 1920x1080@60Hz OLED (Samsung ATNA56WR06) + - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB1) + - 1x HDMI 2.1 + - 1x Mini DisplayPort 1.4 + - 1x DisplayPort 1.4 over USB-C +- Memory + - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 2933 MHz +- Networking + - Gigabit Ethernet + - M.2 PCIe/CNVi WiFi/Bluetooth + - Intel WiFi 6 AX200/AX201 +- Power + - 180W (19.5V, 9.23A) AC barrel adapter + - Chicony A17-180P4A, using a C5 power cord + - 73Wh 3-cell battery +- Sound + - Internal speakers and microphone + - Combined 3.5mm headphone and microphone jack + - Combined 3.5mm microphone and S/PDIF jack + - HDMI, Mini DisplayPort, USB-C DisplayPort audio +- Storage + - 1x M.2 PCIe NVMe or SATA SSD + - 1x M.2 PCIe NVME SSD + - MicroSD card reader +- USB + - 1x USB Type-C with Thunderbolt 3 + - 3x USB 3.2 Gen 1 Type-A +- Dimensions + - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg + - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg + +## Flashing coreboot + +```eval_rst ++---------------------+-----------------+ +| Type | Value | ++=====================+=================+ +| Socketed flash | no | ++---------------------+-----------------+ +| Vendor | Macronix | ++---------------------+-----------------+ +| Model | MX25L12873F | ++---------------------+-----------------+ +| Size | 16 MiB | ++---------------------+-----------------+ +| Package | SOIC-8 | ++---------------------+-----------------+ +| Internal flashing | yes | ++---------------------+-----------------+ +| External flashing | yes | ++---------------------+-----------------+ +``` + +The flash chip (U66) is above the M.2 SSD connectors. diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig index 5a6100c..b4a5903 100644 --- a/src/mainboard/system76/oryp6/Kconfig +++ b/src/mainboard/system76/oryp6/Kconfig @@ -1,4 +1,4 @@ -if BOARD_SYSTEM76_ORYP6 +if BOARD_SYSTEM76_ORYP6 || BOARD_SYSTEM76_ORYP7 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -23,24 +23,28 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP + select TPM_RDRESP_NEED_DELAY config MAINBOARD_DIR default "system76/oryp6" config VARIANT_DIR default "oryp6" if BOARD_SYSTEM76_ORYP6 + default "oryp7" if BOARD_SYSTEM76_ORYP7 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER default "oryp6" if BOARD_SYSTEM76_ORYP6 + default "oryp7" if BOARD_SYSTEM76_ORYP7 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Oryx Pro" config MAINBOARD_VERSION default "oryp6" if BOARD_SYSTEM76_ORYP6 + default "oryp7" if BOARD_SYSTEM76_ORYP7 config CBFS_SIZE default 0xA00000 diff --git a/src/mainboard/system76/oryp6/Kconfig.name b/src/mainboard/system76/oryp6/Kconfig.name index 8012d03..605ca3e 100644 --- a/src/mainboard/system76/oryp6/Kconfig.name +++ b/src/mainboard/system76/oryp6/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_SYSTEM76_ORYP6 bool "oryp6" + +config BOARD_SYSTEM76_ORYP7 + bool "oryp7" diff --git a/src/mainboard/system76/oryp6/Makefile.inc b/src/mainboard/system76/oryp6/Makefile.inc index bc055f8..2267eb6 100644 --- a/src/mainboard/system76/oryp6/Makefile.inc +++ b/src/mainboard/system76/oryp6/Makefile.inc @@ -4,6 +4,7 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c romstage-y += romstage.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += ramstage.c ramstage-y += tas5825m.c diff --git a/src/mainboard/system76/oryp6/include/variant/romstage.h b/src/mainboard/system76/oryp6/include/variant/romstage.h new file mode 100644 index 0000000..072a485 --- /dev/null +++ b/src/mainboard/system76/oryp6/include/variant/romstage.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_ROMSTAGE_H +#define VARIANT_ROMSTAGE_H + +#include <fsp/soc_binding.h> + +void variant_configure_fspm(FSPM_UPD *memupd); + +#endif diff --git a/src/mainboard/system76/oryp6/romstage.c b/src/mainboard/system76/oryp6/romstage.c index 6309e4a..8ea791a 100644 --- a/src/mainboard/system76/oryp6/romstage.c +++ b/src/mainboard/system76/oryp6/romstage.c @@ -2,6 +2,7 @@ #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <variant/romstage.h> static const struct cnl_mb_cfg memcfg = { .spd[0] = { @@ -20,8 +21,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - // Allow memory speeds higher than 2933 MT/s - memupd->FspmConfig.SaOcSupport = 1; + variant_configure_fspm(memupd); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } diff --git a/src/mainboard/system76/oryp6/variants/oryp6/romstage.c b/src/mainboard/system76/oryp6/variants/oryp6/romstage.c new file mode 100644 index 0000000..aa92a5e --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp6/romstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/romstage.h> + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + // Allow memory speeds higher than 2933 MT/s + memupd->FspmConfig.SaOcSupport = 1; +} diff --git a/src/mainboard/system76/oryp6/variants/oryp7/board_info.txt b/src/mainboard/system76/oryp6/variants/oryp7/board_info.txt new file mode 100644 index 0000000..4780b9b --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp7/board_info.txt @@ -0,0 +1,2 @@ +Board name: oryp7 +Release year: 2021 diff --git a/src/mainboard/system76/oryp6/variants/oryp7/data.vbt b/src/mainboard/system76/oryp6/variants/oryp7/data.vbt new file mode 100644 index 0000000..ee4cecd --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp7/data.vbt Binary files differ diff --git a/src/mainboard/system76/oryp6/variants/oryp7/gpio.c b/src/mainboard/system76/oryp6/variants/oryp7/gpio.c new file mode 100644 index 0000000..88fb95a --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp7/gpio.c @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <variant/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT + PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH + PAD_NC(GPD6, NONE), + PAD_CFG_GPI(GPD7, UP_20K, PWROK), /* GPD_7: crystal input + low = single ended, + high = differential + */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK + PAD_NC(GPD9, NONE), + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // SLP_S5# + PAD_NC(GPD11, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0 + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1 + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2 + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // LPC_PIRQA# + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC + PAD_NC(GPP_A10, NONE), + PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WAKEUP# + PAD_CFG_GPO(GPP_A12, 1, DEEP), // ROM_I2C_EN + PAD_NC(GPP_A13, NONE), // SUSWARN# (test point) + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), // SUS_PWR_ACK# (test point) + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), // GPP_A18 (test point) + PAD_CFG_GPO(GPP_A19, 1, DEEP), // SB_BLON + PAD_NC(GPP_A20, NONE), + PAD_CFG_GPI(GPP_A21, UP_20K, DEEP), // EAPD_MODE + PAD_CFG_GPO(GPP_A22, 1, DEEP), // WLAN_SSD2_GPIO1 + PAD_CFG_GPO(GPP_A23, 1, DEEP), // WLAN_SSD2_GPIO + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_B1, NONE), + PAD_NC(GPP_B2, NONE), + PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN + PAD_CFG_GPO(GPP_B4, 1, DEEP), // WLAN_EN + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ# + PAD_CFG_GPI(GPP_B6, NONE, DEEP), // DDS_ID0 + PAD_CFG_GPO(GPP_B7, 1, PLTRST), // CR_GPIO_RST# + PAD_CFG_GPO(GPP_B8, 1, PLTRST), // CR_GPIO_WAKE# + PAD_CFG_GPI(GPP_B9, NONE, DEEP), // DDS_DET + PAD_CFG_GPI(GPP_B10, NONE, DEEP), // GSYNC_DET + PAD_NC(GPP_B11, NONE), + PAD_CFG_GPI(GPP_B12, UP_20K, DEEP), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), // LPSS_GSPI0_MOSI (test point) + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI (boot strap) + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // PCH_HOT_GNSS_DISABLE (boot strap) + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // CNVI_WAKE# + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_CFG_GPI(GPP_C5, UP_20K, DEEP), // WLAN_WAKEUP# + PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), // SMC_CPU_THERM + PAD_CFG_GPI(GPP_C7, UP_20K, DEEP), // SMD_CPU_THERM + PAD_CFG_GPI(GPP_C8, NONE, PLTRST), // TPM_DET + PAD_CFG_GPI(GPP_C9, NONE, DEEP), // CNVI_DET# + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + //PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1# + //PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2# + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C_SDA_Pantone + PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C_SCL_Pantone + PAD_CFG_GPI(GPP_C20, UP_20K, DEEP), // CNVI_MFUART2_RXD + PAD_CFG_GPI(GPP_C21, UP_20K, DEEP), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_C22, UP_20K, DEEP), // LAN_PLT_RST# + PAD_NC(GPP_C23, UP_20K), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF2), // I2C_SDA_PDROM + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST# + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ + PAD_NC(GPP_D7, NONE), // M.2_BT_PCMIN (test point) + PAD_NC(GPP_D8, NONE), // M.2_BT_PCMCLK (test point) + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF2), // I2C_SCL_PDROM + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_PEDET + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI(GPP_E3, NONE, DEEP), // 10k pull up + PAD_NC(GPP_E4, NONE), + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // M2_P1_SATA_DEVSLP + _PAD_CFG_STRUCT(GPP_E6, 0x82040100, 0x0000), // SMI# + PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED# + PAD_NC(GPP_E9, NONE), // USB_OC0# (test point) + PAD_NC(GPP_E10, NONE), // USB_OC1# (test point) + PAD_NC(GPP_E11, NONE), // USB_OC2# (test point) + PAD_NC(GPP_E12, NONE), // USB_OC3# (test point) + + /* ------- GPIO Group GPP_F ------- */ + //PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N + PAD_CFG_GPI(GPP_F1, NONE, DEEP), // M.2_SSD2_PEDET (board error) + PAD_CFG_GPI(GPP_F2, NONE, DEEP), // TBTA_HRESET + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), // PLVDD_RST_EC + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // M2_P4_SATA_DEVSLP (board error) + PAD_NC(GPP_F7, NONE), // BL_PWM_EN_EC + PAD_NC(GPP_F8, NONE), // MUX_CTRL_BIOS + PAD_NC(GPP_F9, NONE), // PS8461_SW + PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // BIOS_REC + PAD_CFG_GPI(GPP_F11, UP_20K, DEEP), // PCH_RSVD + PAD_NC(GPP_F12, NONE), + PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), // GP39_GFX_CRB_DETECT + PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // 10k pull to H_SKTOCC_N + PAD_NC(GPP_F15, NONE), // USB_OC4# (test point) + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), // USB_OC7# (test point) + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + //PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH + //PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI(GPP_G0, DN_20K, DEEP), // BOARD_ID1 + PAD_CFG_GPI(GPP_G1, DN_20K, DEEP), // BOARD_ID2 + PAD_CFG_GPI(GPP_G2, DN_20K, DEEP), // BOARD_ID3 + PAD_CFG_GPI(GPP_G3, DN_20K, DEEP), // BOARD_ID4 + PAD_CFG_GPI(GPP_G4, UP_20K, DEEP), // GPIO4_NVVDD_EN_R + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CLK_REQ7_LAN# + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // CLK_REQ8_PEG# + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // CLK_REQ9_CARD# + _PAD_CFG_STRUCT(GPP_H4, 0x40880100, 0x3000), // RTD3_PCIE_WAKE# + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // CLK_REQ11_SSD2# + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CLK_REQ12_SSD1# + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), // eSPI flash sharing mode strap + PAD_CFG_GPI(GPP_H13, NONE, DEEP), // 100k pull up + PAD_NC(GPP_H14, NONE), + PAD_CFG_GPI(GPP_H15, NONE, DEEP), // 100k pull up + //PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R + PAD_CFG_GPO(GPP_H17, 1, PLTRST), // TBT_FORCE_PWR_R + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H19, 1, DEEP), // GPIO_CARD_AUX + PAD_CFG_GPO(GPP_H20, 1, DEEP), // GPIO_CARD + PAD_CFG_GPI(GPP_H21, UP_20K, DEEP), // 20k pull down, 4.7k pull up + PAD_NC(GPP_H22, NONE), + PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT# + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), + _PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // G_DP_DHPD_E + _PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // OUT2_HPD + PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + _PAD_CFG_STRUCT(GPP_I10, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT + PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // 10k pull to H_SKTOCC_N, 10k pull up + PAD_CFG_GPI(GPP_I12, DN_20K, DEEP), // D02C_BOARD_ID (10k pull up) + PAD_NC(GPP_I13, NONE), + PAD_NC(GPP_I14, NONE), + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_VCCIO_PWR_GATE + PAD_CFG_GPI(GPP_J2, UP_20K, DEEP), // 100k pull down + PAD_NC(GPP_J3, NONE), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // M.2_CNV_BRI_DT_BT_UART0_RTS + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // M.2_CNV_BRI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // M.2_CNV_RGI_DT_BT_UART0_TX + PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // M.2_CNV_RGI_RSP + PAD_NC(GPP_J8, NONE), + PAD_CFG_GPI(GPP_J9, UP_20K, DEEP), // 100k pull up, 100k pull down + PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // 100k pull down + PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), // 75k pull down + + /* ------- GPIO Group GPP_K ------- */ + PAD_NC(GPP_K0, NONE), + PAD_NC(GPP_K1, NONE), + PAD_NC(GPP_K2, NONE), + _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI# + PAD_NC(GPP_K4, NONE), + PAD_NC(GPP_K5, NONE), + _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI# + PAD_NC(GPP_K7, NONE), + //PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1 + //PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2 + PAD_CFG_GPO(GPP_K10, 1, DEEP), // LANRTD3_WAKE# + //PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3 + PAD_NC(GPP_K12, NONE), + PAD_NC(GPP_K13, NONE), + PAD_CFG_GPI(GPP_K14, UP_20K, DEEP), // GPP_K_14_GSXDIN (test point) + PAD_NC(GPP_K15, NONE), + PAD_NC(GPP_K16, NONE), + PAD_NC(GPP_K17, NONE), + PAD_NC(GPP_K18, NONE), + PAD_CFG_GPI(GPP_K19, UP_20K, DEEP), // SMI# + PAD_NC(GPP_K20, NONE), + PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH + PAD_CFG_GPO(GPP_K22, 0, DEEP), // OVRM + PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/oryp6/variants/oryp7/gpio_early.c b/src/mainboard/system76/oryp6/variants/oryp7/gpio_early.c new file mode 100644 index 0000000..cc60c32 --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp7/gpio_early.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <variant/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1# + PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2# + PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N + PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R + PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1 + PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2 + PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3 +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c b/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c new file mode 100644 index 0000000..cc959b8 --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x155865e5, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155865e5), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x04451150), +}; + +const u32 pc_beep_verbs[] = { + // Enable DMIC microphone on ALC1220 + 0x02050036, + 0x02042a6a, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb b/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb new file mode 100644 index 0000000..3be1b15 --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/cannonlake + device domain 0 on + subsystemid 0x1558 0x65e5 inherit + end +end diff --git a/src/mainboard/system76/oryp6/variants/oryp7/romstage.c b/src/mainboard/system76/oryp6/variants/oryp7/romstage.c new file mode 100644 index 0000000..2873dd6 --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp7/romstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/romstage.h> + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + // Typically, we set SaOcSupport to allow overclocking RAM, + // but oryp7 saw a high fail rate when using 3200 MHz DIMMs. + // So disable OC so modules run at the standard 2933 MHz. + memupd->FspmConfig.SaOcSupport = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43 Gerrit-Change-Number: 52296 Gerrit-PatchSet: 15 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/oryp6: Add Oryx Pro 7 as a variant
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52296 ) Change subject: mb/system76/oryp6: Add Oryx Pro 7 as a variant ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43 Gerrit-Change-Number: 52296 Gerrit-PatchSet: 14 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 19:21:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/oryp6: Convert to variant setup
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57786 ) Change subject: mb/system76/oryp6: Convert to variant setup ...................................................................... mb/system76/oryp6: Convert to variant setup The Oryx Pro 6 has the same board layout as the next model in series, Oryx Pro 7. The primary difference between the two is the dGPU (20 series to 30 series). Convert oryp6 to a variant setup in preparation for adding the oryp7. Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/system76/oryp6/Kconfig M src/mainboard/system76/oryp6/Makefile.inc M src/mainboard/system76/oryp6/board_info.txt M src/mainboard/system76/oryp6/bootblock.c M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/oryp6/dsdt.asl D src/mainboard/system76/oryp6/include/mainboard/gpio.h A src/mainboard/system76/oryp6/include/variant/gpio.h M src/mainboard/system76/oryp6/ramstage.c A src/mainboard/system76/oryp6/variants/oryp6/board_info.txt R src/mainboard/system76/oryp6/variants/oryp6/data.vbt R src/mainboard/system76/oryp6/variants/oryp6/gpio.c R src/mainboard/system76/oryp6/variants/oryp6/gpio_early.c R src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c A src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb 15 files changed, 52 insertions(+), 46 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig index eeed385..5a6100c 100644 --- a/src/mainboard/system76/oryp6/Kconfig +++ b/src/mainboard/system76/oryp6/Kconfig @@ -27,41 +27,40 @@ config MAINBOARD_DIR default "system76/oryp6" +config VARIANT_DIR + default "oryp6" if BOARD_SYSTEM76_ORYP6 + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER - default "oryp6" + default "oryp6" if BOARD_SYSTEM76_ORYP6 config MAINBOARD_SMBIOS_PRODUCT_NAME - string default "Oryx Pro" config MAINBOARD_VERSION - string - default "oryp6" + default "oryp6" if BOARD_SYSTEM76_ORYP6 config CBFS_SIZE default 0xA00000 config CONSOLE_POST - bool default y config ONBOARD_VGA_IS_PRIMARY - bool default y config MAX_CPUS - int default 16 config DIMM_MAX default 2 config VGA_BIOS_ID - string default "8086,9bc4" config POST_DEVICE - bool default n endif diff --git a/src/mainboard/system76/oryp6/Makefile.inc b/src/mainboard/system76/oryp6/Makefile.inc index 7c0701e..bc055f8 100644 --- a/src/mainboard/system76/oryp6/Makefile.inc +++ b/src/mainboard/system76/oryp6/Makefile.inc @@ -1,9 +1,11 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include bootblock-y += bootblock.c -bootblock-y += gpio_early.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += romstage.c ramstage-y += ramstage.c -ramstage-y += gpio.c -ramstage-y += hda_verb.c ramstage-y += tas5825m.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/oryp6/board_info.txt b/src/mainboard/system76/oryp6/board_info.txt index 94017b9..badfb66 100644 --- a/src/mainboard/system76/oryp6/board_info.txt +++ b/src/mainboard/system76/oryp6/board_info.txt @@ -1,7 +1,5 @@ Vendor name: System76 -Board name: oryp6 Category: laptop -Release year: 2020 ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/system76/oryp6/bootblock.c b/src/mainboard/system76/oryp6/bootblock.c index d75158c..0dc25dd 100644 --- a/src/mainboard/system76/oryp6/bootblock.c +++ b/src/mainboard/system76/oryp6/bootblock.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <gpio.h> -#include <mainboard/gpio.h> +#include <variant/gpio.h> void bootblock_mainboard_init(void) { - mainboard_configure_early_gpios(); + variant_configure_early_gpios(); } diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 56b08fb..8fc274b 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -57,7 +57,6 @@ end device domain 0 on - subsystemid 0x1558 0x50d3 inherit device pci 00.0 on end # Host Bridge device pci 01.0 on # GPU Port # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) @@ -98,7 +97,7 @@ end end device pci 14.5 off end # SDCard - device pci 15.0 on + device pci 15.0 on # I2C #0 chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" @@ -107,7 +106,7 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end - end # I2C #0 + end device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 diff --git a/src/mainboard/system76/oryp6/dsdt.asl b/src/mainboard/system76/oryp6/dsdt.asl index 8a3b4d7..d2bd57d 100644 --- a/src/mainboard/system76/oryp6/dsdt.asl +++ b/src/mainboard/system76/oryp6/dsdt.asl @@ -7,7 +7,7 @@ ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 /* OEM revision */ + 0x20110725 ) { #include <acpi/dsdt_top.asl> diff --git a/src/mainboard/system76/oryp6/include/mainboard/gpio.h b/src/mainboard/system76/oryp6/include/mainboard/gpio.h deleted file mode 100644 index c6393be..0000000 --- a/src/mainboard/system76/oryp6/include/mainboard/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -void mainboard_configure_early_gpios(void); -void mainboard_configure_gpios(void); - -#endif diff --git a/src/mainboard/system76/oryp6/include/variant/gpio.h b/src/mainboard/system76/oryp6/include/variant/gpio.h new file mode 100644 index 0000000..95d5762 --- /dev/null +++ b/src/mainboard/system76/oryp6/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/oryp6/ramstage.c b/src/mainboard/system76/oryp6/ramstage.c index 43ee54f..ca6f64b1 100644 --- a/src/mainboard/system76/oryp6/ramstage.c +++ b/src/mainboard/system76/oryp6/ramstage.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> -#include <mainboard/gpio.h> +#include <variant/gpio.h> static void mainboard_init(void *chip_info) { - mainboard_configure_gpios(); + variant_configure_gpios(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/system76/oryp6/variants/oryp6/board_info.txt b/src/mainboard/system76/oryp6/variants/oryp6/board_info.txt new file mode 100644 index 0000000..2d0fb19 --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp6/board_info.txt @@ -0,0 +1,2 @@ +Board name: oryp6 +Release year: 2020 diff --git a/src/mainboard/system76/oryp6/data.vbt b/src/mainboard/system76/oryp6/variants/oryp6/data.vbt similarity index 100% rename from src/mainboard/system76/oryp6/data.vbt rename to src/mainboard/system76/oryp6/variants/oryp6/data.vbt Binary files differ diff --git a/src/mainboard/system76/oryp6/gpio.c b/src/mainboard/system76/oryp6/variants/oryp6/gpio.c similarity index 94% rename from src/mainboard/system76/oryp6/gpio.c rename to src/mainboard/system76/oryp6/variants/oryp6/gpio.c index f83d73e..efdb79f 100644 --- a/src/mainboard/system76/oryp6/gpio.c +++ b/src/mainboard/system76/oryp6/variants/oryp6/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <mainboard/gpio.h> #include <soc/gpio.h> +#include <variant/gpio.h> static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPD ------- */ @@ -88,8 +88,8 @@ PAD_NC(GPP_C11, NONE), PAD_NC(GPP_C12, NONE), PAD_NC(GPP_C13, NONE), - PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1# - PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2# + //PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1# + //PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2# PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C_SDA_Pantone @@ -141,7 +141,7 @@ PAD_NC(GPP_E12, NONE), // USB_OC3# (test point) /* ------- GPIO Group GPP_F ------- */ - PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N + //PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N PAD_CFG_GPI(GPP_F1, NONE, DEEP), // M.2_SSD2_PEDET (board error) PAD_CFG_GPI(GPP_F2, NONE, DEEP), // TBTA_HRESET PAD_NC(GPP_F3, NONE), @@ -163,8 +163,8 @@ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS - PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH - PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + //PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH + //PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN /* ------- GPIO Group GPP_G ------- */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1 @@ -193,7 +193,7 @@ PAD_CFG_GPI(GPP_H13, NONE, DEEP), // 100k pull up PAD_NC(GPP_H14, NONE), PAD_CFG_GPI(GPP_H15, NONE, DEEP), // 20k pull up - PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R + //PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R PAD_CFG_GPO(GPP_H17, 1, PLTRST), // TBT_FORCE_PWR_R PAD_NC(GPP_H18, NONE), PAD_CFG_GPO(GPP_H19, 1, DEEP), // GPIO_CARD_AUX @@ -242,10 +242,10 @@ PAD_NC(GPP_K5, NONE), _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI# PAD_NC(GPP_K7, NONE), - PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1 - PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2 + //PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1 + //PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2 PAD_CFG_GPO(GPP_K10, 1, DEEP), // LANRTD3_WAKE# - PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3 + //PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3 PAD_NC(GPP_K12, NONE), PAD_NC(GPP_K13, NONE), PAD_NC(GPP_K14, NONE), // GPP_K_14_GSXDIN (test point) @@ -260,7 +260,7 @@ PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R }; -void mainboard_configure_gpios(void) +void variant_configure_gpios(void) { gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } diff --git a/src/mainboard/system76/oryp6/gpio_early.c b/src/mainboard/system76/oryp6/variants/oryp6/gpio_early.c similarity index 77% rename from src/mainboard/system76/oryp6/gpio_early.c rename to src/mainboard/system76/oryp6/variants/oryp6/gpio_early.c index c71ee25..cc60c32 100644 --- a/src/mainboard/system76/oryp6/gpio_early.c +++ b/src/mainboard/system76/oryp6/variants/oryp6/gpio_early.c @@ -1,19 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <mainboard/gpio.h> #include <soc/gpio.h> +#include <variant/gpio.h> static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_C14, 1, RSMRST), // M.2_PLT_RST_CNTRL1# PAD_CFG_GPO(GPP_C15, 1, RSMRST), // M.2_PLT_RST_CNTRL2# PAD_CFG_GPO(GPP_F0, 1, RSMRST), // TBT_PERST_N + PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R PAD_CFG_GPO(GPP_K8, 1, RSMRST), // SATA_M2_PWR_EN1 PAD_CFG_GPO(GPP_K9, 1, RSMRST), // SATA_M2_PWR_EN2 - PAD_CFG_GPO(GPP_H16, 1, RSMRST), // TBT_RTD3_PWR_EN_R PAD_CFG_GPO(GPP_K11, 1, RSMRST), // GPIO_LANRTD3 }; -void mainboard_configure_early_gpios(void) +void variant_configure_early_gpios(void) { gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } diff --git a/src/mainboard/system76/oryp6/hda_verb.c b/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c similarity index 100% rename from src/mainboard/system76/oryp6/hda_verb.c rename to src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c diff --git a/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb b/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb new file mode 100644 index 0000000..3d6355e --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/cannonlake + device domain 0 on + subsystemid 0x1558 0x50d3 inherit + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/57786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed Gerrit-Change-Number: 57786 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/oryp6: Convert to variant setup
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57786 ) Change subject: mb/system76/oryp6: Convert to variant setup ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed Gerrit-Change-Number: 57786 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 19:21:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/kbl-u: Add System76 Galago Pro 3 Rev B
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52217 ) Change subject: mb/system76/kbl-u: Add System76 Galago Pro 3 Rev B ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25464d3a2dd02e613a8392db90b1eaf0f9b3ca70 Gerrit-Change-Number: 52217 Gerrit-PatchSet: 10 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 19:18:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Use dedicated VBT files for ADL-M
by Selma Bensaid (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Tim Wawrzynczak. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58202 ) Change subject: mb/intel/adlrvp: Use dedicated VBT files for ADL-M ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f Gerrit-Change-Number: 58202 Gerrit-PatchSet: 3 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 19:11:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci_rom: Add vga_oprom_preload
by Raul Rangel (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Furquan Shaikh, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56581 ) Change subject: device/pci_rom: Add vga_oprom_preload ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: This plus the rest of the patches on top are ready to review. -- To view, visit https://review.coreboot.org/c/coreboot/+/56581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb54fe3a942e9507ff6f1173ba5620a8f4ce6549 Gerrit-Change-Number: 56581 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 19:07:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/lib: Support fallback option for fw_config
by Wonkyu Kim (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Furquan Shaikh, Jamie Ryu, Ravishankar Sarawadi, Tim Wawrzynczak, Subrata Banik, Julius Werner, Nick Vaccaro, Raj Astekar, Srinidhi N Kaushik. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58833 ) Change subject: src/lib: Support fallback option for fw_config ...................................................................... Patch Set 5: (2 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/58833/comment/6ece5685_1c716d28 PS4, Line 408: FW_CONFIG_SOURCE_CBFS > why can't FW_CONFIG_SOURCE_CBFS Kconfig exist in line 398 above ? Changing sequence is for following fallback order. Current fallback order is FW_CONFIG_SOURCE_CHROMEEC_CBI and FW_CONFIG_SOURCE_CBFS https://review.coreboot.org/c/coreboot/+/58833/comment/73479831_3e34cfd9 PS4, Line 416: and > remove one "and"? […] Will remove "and". FW_CONFIG_SOURCE_CBFS can be fallback option after FW_CONFIG_SOURCE_CHROMEEC_CBI. -- To view, visit https://review.coreboot.org/c/coreboot/+/58833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff Gerrit-Change-Number: 58833 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 19:01:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021