coreboot-gerrit November 2021

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Change in coreboot[master]: sc7280: Add CPUCP firmware support
by Ravi kumar (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Ravi kumar, Ravi Kumar Bokka. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49768 to look at the new patch set (#85). Change subject: sc7280: Add CPUCP firmware support ...................................................................... sc7280: Add CPUCP firmware support CPUCP is CPUSS Control Processor. It refers to the firmware for control CPUSS active power management. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/cpucp_load_reset.c A src/soc/qualcomm/sc7280/include/soc/cpucp.h M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 6 files changed, 99 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49768/85 -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 85 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Reka Norman (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 ) Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: It’s been bothering me how ADL-specific this implementation is. E.g. not including tCKmax or the CAS latencies as attributes since the ADL MRC doesn’t use them, assuming 4:1 WCK:CK and 8B bank mode only, etc. My reasoning is that it’s not worth trying to generalise the code at this stage since I have no idea what the commonalities and differences between platforms will be. This is partly because there’s no LP5 SPD spec, so there’s a lot of room for SoC vendors to make their own decisions. I would assume future Intel platforms will be relatively similar to ADL, but if we have any AMD platforms using LP5 they could do something very different. So my plan is to just wait and see what other platforms do, and generalise the code as needed then. If anyone has thoughts on this, let me know. -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 8 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 03 Nov 2021 00:17:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/psp_verstage: Init TPM on S0i3 resume
by build bot (Jenkins) (Code Review) 03 Nov '21

03 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58870 ) Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/psp_verstage/psp_verstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132077): https://review.coreboot.org/c/coreboot/+/58870/comment/66663be7_0714b9b5 PS1, Line 276: if(retval) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Nov 2021 00:15:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/psp_verstage: Init TPM on S0i3 resume
by Rob Barnes (Code Review) 03 Nov '21

03 Nov '21

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58870 ) Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... soc/amd/psp_verstage: Init TPM on S0i3 resume Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. The PSP is handling restoring everything else, so only the minimum TPM initialize is done. BUG=b:200578885 TEST=Multiple cycles of S0i3 suspend resume BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c M src/vendorcode/google/chromeos/Kconfig 4 files changed, 63 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58870/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 46e6017..c3eef3f 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -389,6 +389,15 @@ help Add psp_verstage signature token to the build & PSP Directory Table +config PSP_INIT_TPM_ON_S0I3_RESUME + bool + default y + depends on TPM2 && VBOOT_STARTS_BEFORE_BOOTBLOCK + help + If the TPM is reset while in S0i3, it must be restored during s0i3 + resume. This must be performed in PSP verstage since coreboot is + otherwise not involved with s0i3 resume. + endmenu config VBOOT diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index be6b23d..6f240ee 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -23,6 +23,8 @@ #define POSTCODE_SAVE_BUFFERS 0x0E #define POSTCODE_UPDATE_BOOT_REGION 0x0F +#define POSTCODE_VERSTAGE_S0I3_RESUME 0x10 + #define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0 #define POSTCODE_WORKBUF_RESIZE_WARNING 0xC1 #define POSTCODE_WORKBUF_SAVE_ERROR 0xC2 @@ -34,6 +36,7 @@ #define POSTCODE_FMAP_REGION_MISSING 0xC8 #define POSTCODE_AMD_FW_MISSING 0xC9 #define POSTCODE_CMOS_RECOVERY 0xCA +#define POSTCODE_INIT_TPM_FAILED 0xCB #define POSTCODE_UNMAP_SPI_ROM 0xF0 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1 diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 5c59c4f..1b4ab52 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -5,14 +5,18 @@ #include <amdblocks/acpimmio.h> #include <bl_uapp/bl_syscall_public.h> #include <boot_device.h> +#include <bootstate.h> #include <cbfs.h> #include <console/console.h> #include <fmap.h> #include <pc80/mc146818rtc.h> #include <soc/psp_transfer.h> +#include <security/tpm/tspi.h> +#include <security/tpm/tss.h> #include <security/vboot/vbnv.h> #include <security/vboot/misc.h> #include <security/vboot/symbols.h> +#include <security/vboot/tpm_common.h> #include <security/vboot/vboot_common.h> #include <arch/stages.h> #include <stdarg.h> @@ -196,10 +200,44 @@ return 0; } +/** + * S0i3 resume in PSP verstage is a special case. The PSP is restoring + * everything except the TPM. So do the minimum needed to re-initialize the TPM. + */ +static uint32_t psp_verstage_s0i3_resume(void) +{ + uint32_t rv = 0; + + post_code(POSTCODE_VERSTAGE_S0I3_RESUME); + + if (!CONFIG(PSP_INIT_TPM_ON_S0I3_RESUME)) + return rv; + + printk(BIOS_DEBUG, "Entering PSP verstage S0i3 resume\n"); + + rv = tpm_setup(true); + if (rv != TPM_SUCCESS) { + printk(BIOS_ERR, "tpm_setup failed rv:%d\n", rv); + return POSTCODE_INIT_TPM_FAILED; + } + + if (CONFIG(CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME)) { + rv = tlcl_disable_platform_hierarchy(); + if (rv != TPM_SUCCESS) { + printk(BIOS_ERR, "tlcl_disable_platform_hierarchy failed rv:%d\n", rv); + return POSTCODE_INIT_TPM_FAILED; + } + } + + return rv; +} + void Main(void) { uint32_t retval; struct vb2_context *ctx = NULL; + uint32_t bootmode; + /* * Do not use printk() before console_init() @@ -230,6 +268,18 @@ post_code(POSTCODE_VERSTAGE_MAIN); + svc_get_boot_mode(&bootmode); + + /* S0i3 resume in PSP verstage is a special case. */ + if (bootmode == PSP_BOOT_MODE_S0i3_RESUME) { + retval = psp_verstage_s0i3_resume(); + if(retval) + reboot_into_recovery(ctx, retval); + post_code(POSTCODE_UNMAP_FCH_DEVICES); + unmap_fch_devices(); + svc_exit(retval); + } + vboot_run_logic(); ctx = vboot_get_context(); diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 605b09e..3f2d6a1 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -44,7 +44,7 @@ config CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME bool default y - depends on TPM2 && RESUME_PATH_SAME_AS_BOOT + depends on TPM2 help Disable the platform heirarchy on resume path if the firmware is involved in resume. The hierarchy is disabled prior to jumping -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Use dedicated VBT files for ADL-M
by Bora Guvendik (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Tim Wawrzynczak. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58202 ) Change subject: mb/intel/adlrvp: Use dedicated VBT files for ADL-M ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f Gerrit-Change-Number: 58202 Gerrit-PatchSet: 3 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 23:48:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries
by Angel Pons (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Nico Huber, Martin Roth, Furquan Shaikh, Paul Menzel, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57370 ) Change subject: SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57370/comment/f05bb8eb_e1ffd40d PS4, Line 35: Although the preprocessor usage isn't particularly elegant, adjusting : the devicetree syntax and/or grammar depending on a Kconfig option is : probably even worse. > > similar to the linked list of PCIe capabilities? > > Not sure if I follow. Do you mean the PCI config-space thing? Yes, that. -- To view, visit https://review.coreboot.org/c/coreboot/+/57370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Gerrit-Change-Number: 57370 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 23:37:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Reka Norman (Code Review) 02 Nov '21

02 Nov '21

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Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Reka Norman (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Hello build bot (Jenkins), Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58679 to look at the new patch set (#8). Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... util/spd_tools: Add LP5 support for ADL Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is supported. The SPDs are generated based on a combination of: - The LPDDR5 spec JESD209-5B. - The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5). - Intel recommendations in advisory #616599. BUG=b:201234943, b:198704251 TEST=Generate the SPD and manifests for a test part, and check that the SPD matches Intel's expectation. More details in CB:58680. Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M util/spd_tools/README.md M util/spd_tools/src/part_id_gen/part_id_gen.go A util/spd_tools/src/spd_gen/lp5.go M util/spd_tools/src/spd_gen/spd_gen.go 4 files changed, 726 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/58679/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 8 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LPDDR5
by Cliff Huang (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Anil Kumar K, Selma Bensaid, Paul Menzel, Tim Wawrzynczak, Angel Pons, Sridhar Siricilla, Bernardo Perez Priego. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58101 ) Change subject: lib/spd_bin: Fix for LPDDR5 ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58101/comment/56d4e343_a74ac864 PS8, Line 7: Fix for LPDDR5 > Please also make this a statement, and maybe use *Update*: […] okay. will make the change. File src/lib/spd_bin.c: https://review.coreboot.org/c/coreboot/+/58101/comment/3f5227df_bf70c2ce PS8, Line 27: use_ddr4_ddr5_params > Why do you think this name could be better? Not hearing Paul back. How about changing this function like use_ddr3_params() and reverting the logic? One thing left is that: case SPD_DRAM_LPDDR3_JEDEC: This also returns 'true' as ddr4 and ddr5 variants. The is no perfect name for this, but use_ddr3_params() seems a bit better. -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 23:29:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/amd/common/fsp: check FSP binary version.
by build bot (Jenkins) (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Julian Schroeder, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58869 ) Change subject: src/soc/amd/common/fsp: check FSP binary version. ...................................................................... Patch Set 1: (3 comments) File src/drivers/intel/fsp2_0/util.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132074): https://review.coreboot.org/c/coreboot/+/58869/comment/04aa6980_73dbfb1f PS1, Line 80: struct fsp_info_header *info = (struct fsp_info_header *) (fsp_file + FSP_INFO_HEADER_OFF); line over 96 characters File src/soc/amd/common/fsp/fsp_validate.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132074): https://review.coreboot.org/c/coreboot/+/58869/comment/a093be15_a42e0550 PS1, Line 30: printk(BIOS_ERR, "#include file ImageRevisionMajorVersion=%d\n", IMAGE_REVISION_MAJOR_VERSION); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132074): https://review.coreboot.org/c/coreboot/+/58869/comment/8d9eb2ca_7a5a4b4d PS1, Line 37: printk(BIOS_ERR, "#include file ImageRevisionMinorVersion=%d\n", IMAGE_REVISION_MINOR_VERSION); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/58869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646 Gerrit-Change-Number: 58869 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 21:42:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021