coreboot-gerrit November 2021

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Change in coreboot[master]: src/soc/amd/common/fsp: check FSP binary version.
by Name of user not set (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Julian Schroeder. Hello Julian Schroeder, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58869 to review the following change. Change subject: src/soc/amd/common/fsp: check FSP binary version. ...................................................................... src/soc/amd/common/fsp: check FSP binary version. The FSP encodes image revision data that is use to determine if the coreboot header file fspmupd.h and the binary are com- patible. If the image revision major version does not match coreboot will die(). In case of of image revision minor version not matching, only a warning is output. BUG=b:184650244 TEST=verify image revision output in the coreboot serial log. compare to FSP version shown in serial debug output. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646 --- M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/util.c M src/soc/amd/common/fsp/fsp_validate.c M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 5 files changed, 67 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58869/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 5b6318c..85e4c3f 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -10,7 +10,7 @@ #define FSP_HDR_ATTRIB_FSPT 1 #define FSP_HDR_ATTRIB_FSPM 2 #define FSP_HDR_ATTRIB_FSPS 3 - +//jsd #if CONFIG(PLATFORM_USES_FSP2_X86_32) struct fsp_header { uint32_t fsp_revision; @@ -30,6 +30,29 @@ char image_id[sizeof(uint64_t) + 1]; uint8_t revision; } __packed; + +#define FSP_INFO_HEADER_OFF 0x94 +struct fsp_info_header { +uint32_t signature; //FSPH +uint32_t header_length; +uint8_t res1[3]; +uint8_t header_revision; +uint32_t image_revision; +char image_id[8]; +uint32_t image_size; +uint32_t image_base; +uint32_t image_attribute; +uint32_t cfg_region_offset; +uint32_t cfg_region_size; +uint32_t api_entry_num; +uint32_t temp_ram_init_entry_offset; //initial stack +uint32_t fsp_init_entry_offset; +uint32_t notify_phase_entry_offset; +uint32_t fsp_memory_init_entry_offset; +uint32_t temp_ram_exit_entry_offset; +uint32_t fsp_silicon_init_entry_offset; +} __packed; + #else #error You need to implement this struct for x86_64 FSP #endif diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d05b644..cdec105 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -109,7 +109,7 @@ void fsp_verify_upd_header_signature(uint64_t upd_signature, uint64_t expected_signature); void lb_string_platform_blob_version(struct lb_header *header); void report_fspt_output(void); -void soc_validate_fspm_header(const struct fsp_header *hdr); +void soc_validate_fspm_header(const struct fsp_info_header *hdr); /* Fill in header and validate a loaded FSP component. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, void *fsp_blob, size_t size); diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 1128013..e0818d6 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -77,6 +77,7 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, void *fsp_file, size_t file_size) { void *raw_hdr = fsp_file + FSP_HDR_OFFSET; + struct fsp_info_header *info = (struct fsp_info_header *) (fsp_file + FSP_INFO_HEADER_OFF); if (file_size < FSP_HDR_OFFSET + fsp_hdr_get_expected_min_length()) { printk(BIOS_CRIT, "FSP blob too small.\n"); @@ -98,7 +99,7 @@ } if (ENV_ROMSTAGE) - soc_validate_fspm_header(hdr); + soc_validate_fspm_header(info); return CB_SUCCESS; } @@ -224,6 +225,6 @@ memcpy(rec->string, fsp_version, len+1); } -__weak void soc_validate_fspm_header(const struct fsp_header *hdr) +__weak void soc_validate_fspm_header(const struct fsp_info_header *hdr) { } diff --git a/src/soc/amd/common/fsp/fsp_validate.c b/src/soc/amd/common/fsp/fsp_validate.c index 4d6a8f7..dba11ce 100644 --- a/src/soc/amd/common/fsp/fsp_validate.c +++ b/src/soc/amd/common/fsp/fsp_validate.c @@ -4,9 +4,42 @@ #include <fsp/util.h> #include <types.h> + +struct amd_image_revision { +uint8_t build; +uint8_t revision; +uint8_t minor; +uint8_t major; +}; + /* Validate the FSP-M header in romstage */ -void soc_validate_fspm_header(const struct fsp_header *hdr) +void soc_validate_fspm_header(const struct fsp_info_header *hdr) { + struct amd_image_revision *rev = (struct amd_image_revision *) &(hdr->image_revision); + + /* a coding bug on the AMD FSP side makes this value 1 in current versions of the FSP. + Update pushed. */ + if (hdr->image_revision != 1) { + printk(BIOS_ERR, "FSPM major=%d\n", rev->major); + printk(BIOS_ERR, "FSPM minor=%d\n", rev->minor); + printk(BIOS_ERR, "FSPM revision=%d\n", rev->revision); + printk(BIOS_ERR, "FSPM build=%d\n", rev->build); + + if (rev->major != IMAGE_REVISION_MAJOR_VERSION) { + printk(BIOS_ERR, "FSPM binary and fspmupd.h header file IMAGE_REVISION_MAJOR_VERSION don't match.\n"); + printk(BIOS_ERR, "#include file ImageRevisionMajorVersion=%d\n", IMAGE_REVISION_MAJOR_VERSION); + printk(BIOS_ERR, "Please update FspmUpd.h based on the corresponding FSP build's FspmUpd.h\n"); + die("Goodbye now\n"); + } + + if (rev->minor != IMAGE_REVISION_MINOR_VERSION) { + printk(BIOS_ERR, "FSPM binary and fspmupd.h header file version don't match.\n"); + printk(BIOS_ERR, "#include file ImageRevisionMinorVersion=%d\n", IMAGE_REVISION_MINOR_VERSION); + printk(BIOS_ERR, "Please update FspmUpd.h based on the corresponding FSP build's FspmUpd.h\n"); + } + } else + printk(BIOS_ERR, "No AMD FSP image revision information available\n"); + /* Check if the image fits into the reserved memory region */ if (hdr->image_size > CONFIG_FSP_M_SIZE) die("The FSP-M binary is %u bytes larger than the memory region allocated for " diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index f21ca42..f42ed43 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -107,4 +107,9 @@ /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; } FSPM_UPD; +#define IMAGE_REVISION_MAJOR_VERSION 0x01 +#define IMAGE_REVISION_MINOR_VERSION 0x00 +#define IMAGE_REVISION_REVISION 0x05 +#define IMAGE_REVISION_BUILD_NUMBER 0x00 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/58869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646 Gerrit-Change-Number: 58869 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/*: Enable HECI device
by Jeremy Soller (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Tim Crawford. Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58670 ) Change subject: mb/system76/*: Enable HECI device ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0 Gerrit-Change-Number: 58670 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 21:34:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/cpu: handle mp_init_with_smm failure
by Felix Held (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58859 to look at the new patch set (#3). Change subject: soc/amd/*/cpu: handle mp_init_with_smm failure ...................................................................... soc/amd/*/cpu: handle mp_init_with_smm failure When the mp_init_with_smm call returns a failure, coreboot can't just continue with the initialization and boot process due to the system being in a bad state. Ignoring the failure here would just cause the boot process failing elsewhere where it may not be obvious that the failed multi-processor initialization step was the root cause of that. I'm not 100% sure if calling do_cold_reset or calling die_with_post_code is the better option here. Calling do_cold_reset likely here would likely result in a boot-failure loop, so I call die_with_post_code here. BUG=b:193809448 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/stoneyridge/cpu.c 3 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/58859/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Gerrit-Change-Number: 58859 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation/releases/4.15: Add more System76 boards
by Tim Crawford (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Tim Crawford, Jason Glenesk. Hello build bot (Jenkins), Patrick Georgi, Jason Glenesk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58868 to look at the new patch set (#2). Change subject: Documentation/releases/4.15: Add more System76 boards ...................................................................... Documentation/releases/4.15: Add more System76 boards Most of the System76 boards have now been merged. Change-Id: I0353b28c1df3da8be961cb43225dcf9e30b47d16 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M Documentation/releases/coreboot-4.15-relnotes.md 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/58868/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0353b28c1df3da8be961cb43225dcf9e30b47d16 Gerrit-Change-Number: 58868 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/system76/oryp8: Add System76 Oryx Pro 8
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57652 ) Change subject: mb/system76/oryp8: Add System76 Oryx Pro 8 ...................................................................... mb/system76/oryp8: Add System76 Oryx Pro 8 https://tech-docs.system76.com/models/oryp8/README.html Tested with TianoCore (UeifPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone & microphone jack - Combined 3.5mm microphone & S/PDIF jack* - S3 suspend/resume - Booting to Pop!_OS Linux 21.10 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57652 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/oryp8.md A src/mainboard/system76/oryp8/Kconfig A src/mainboard/system76/oryp8/Kconfig.name A src/mainboard/system76/oryp8/Makefile.inc A src/mainboard/system76/oryp8/acpi/mainboard.asl A src/mainboard/system76/oryp8/acpi/sleep.asl A src/mainboard/system76/oryp8/board_info.txt A src/mainboard/system76/oryp8/bootblock.c A src/mainboard/system76/oryp8/cmos.default A src/mainboard/system76/oryp8/cmos.layout A src/mainboard/system76/oryp8/data.vbt A src/mainboard/system76/oryp8/devicetree.cb A src/mainboard/system76/oryp8/dsdt.asl A src/mainboard/system76/oryp8/gpio.c A src/mainboard/system76/oryp8/gpio_early.c A src/mainboard/system76/oryp8/hda_verb.c A src/mainboard/system76/oryp8/include/mainboard/gpio.h A src/mainboard/system76/oryp8/ramstage.c A src/mainboard/system76/oryp8/romstage.c A src/mainboard/system76/oryp8/tas5825m.c 21 files changed, 2,696 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 77af473..f3455ccd 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -193,6 +193,7 @@ - [Oryx Pro 5](system76/oryp5.md) - [Oryx Pro 6](system76/oryp6.md) - [Oryx Pro 7](system76/oryp7.md) +- [Oryx Pro 8](system76/oryp8.md) ## Texas Instruments diff --git a/Documentation/mainboard/system76/oryp8.md b/Documentation/mainboard/system76/oryp8.md new file mode 100644 index 0000000..cfd59d0 --- /dev/null +++ b/Documentation/mainboard/system76/oryp8.md @@ -0,0 +1,70 @@ +# System76 Oryx Pro 8 (oryp8) + +## Specs + +- CPU + - Intel Core i7-11800H +- Chipset + - Intel HM570 +- EC + - ITE IT570E running [System76 EC](https://github.com/system76/ec) +- Graphics + - dGPU options + - NVIDIA GeForce RTX 3070 (Max-Q) + - NVIDIA GeForce RTX 3080 (Max-Q) + - eDP options + - 15.6" 1920x1080@144Hz LCD (LG LP156WFG-SPB3) + - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3) + - 1x HDMI 2.1 + - 1x Mini DisplayPort 1.4 + - 1x DisplayPort 1.4 over USB-C +- Memory + - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz +- Networking + - Gigabit Ethernet + - M.2 PCIe/CNVi WiFi/Bluetooth + - Intel Wi-Fi 6 AX200/AX201 +- Power + - 180W (19.5V, 9.23A) AC barrel adapter + - Lite-On PA-1181-16, using a C5 power cord + - 73Wh 3-cell battery +- Sound + - Realtek ALC1220 codec + - TI TAS5825M smart amp + - Internal speakers and microphone + - Combined 3.5mm headphone & microphone jack + - Combined 3.5mm microphone & S/PDIF jack + - HDMI, mDP, USB-C DP audio +- Storage + - 1x M.2 PCIe NVMe Gen 4 SSD + - 1x M.2 PCIe NVMe Gen 3 or SATA SSD +- USB + - 1x USB Type-C with Thunderbolt 4 + - 3x USB 3.0 Type-A +- Dimensions + - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg + - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg + +## Flashing coreboot + +```eval_rst ++---------------------+-----------------+ +| Type | Value | ++=====================+=================+ +| Socketed flash | no | ++---------------------+-----------------+ +| Vendor | GigaDevice | ++---------------------+-----------------+ +| Model | GD25B127D | ++---------------------+-----------------+ +| Size | 16 MiB | ++---------------------+-----------------+ +| Package | SOIC-8 | ++---------------------+-----------------+ +| Internal flashing | yes | ++---------------------+-----------------+ +| External flashing | yes | ++---------------------+-----------------+ +``` + +The flash chip (U74) is right of the bottom DIMM slot. diff --git a/src/mainboard/system76/oryp8/Kconfig b/src/mainboard/system76/oryp8/Kconfig new file mode 100644 index 0000000..6c9ff4e --- /dev/null +++ b/src/mainboard/system76/oryp8/Kconfig @@ -0,0 +1,66 @@ +if BOARD_SYSTEM76_ORYP8 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select DRIVERS_I2C_TAS5825M + select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_BAT_THRESHOLDS + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_HOTPLUG + select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G + select SOC_INTEL_TIGERLAKE + select SOC_INTEL_TIGERLAKE_PCH_H + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_RDRESP_NEED_DELAY + +config MAINBOARD_DIR + default "system76/oryp8" + +config MAINBOARD_PART_NUMBER + default "oryp8" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Oryx Pro" + +config MAINBOARD_VERSION + default "oryp8" + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config DIMM_MAX + default 4 + +config DIMM_SPD_SIZE + default 512 + +config ONBOARD_VGA_IS_PRIMARY + default y + +config POST_DEVICE + default n + +config UART_FOR_CONSOLE + default 2 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/system76/oryp8/Kconfig.name b/src/mainboard/system76/oryp8/Kconfig.name new file mode 100644 index 0000000..236b8c8 --- /dev/null +++ b/src/mainboard/system76/oryp8/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SYSTEM76_ORYP8 + bool "oryp8" diff --git a/src/mainboard/system76/oryp8/Makefile.inc b/src/mainboard/system76/oryp8/Makefile.inc new file mode 100644 index 0000000..c9b4d07 --- /dev/null +++ b/src/mainboard/system76/oryp8/Makefile.inc @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c +ramstage-y += tas5825m.c diff --git a/src/mainboard/system76/oryp8/acpi/mainboard.asl b/src/mainboard/system76/oryp8/acpi/mainboard.asl new file mode 100644 index 0000000..4675bc9 --- /dev/null +++ b/src/mainboard/system76/oryp8/acpi/mainboard.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#include <ec/system76/ec/acpi/ec.asl> + +Scope (\_SB) { + #include "sleep.asl" +} diff --git a/src/mainboard/system76/oryp8/acpi/sleep.asl b/src/mainboard/system76/oryp8/acpi/sleep.asl new file mode 100644 index 0000000..83888f3 --- /dev/null +++ b/src/mainboard/system76/oryp8/acpi/sleep.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/gpio.h> + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + } +} diff --git a/src/mainboard/system76/oryp8/board_info.txt b/src/mainboard/system76/oryp8/board_info.txt new file mode 100644 index 0000000..544c341 --- /dev/null +++ b/src/mainboard/system76/oryp8/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: oryp8 +Category: laptop +Release year: 2021 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/oryp8/bootblock.c b/src/mainboard/system76/oryp8/bootblock.c new file mode 100644 index 0000000..6b88360 --- /dev/null +++ b/src/mainboard/system76/oryp8/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/system76/oryp8/cmos.default b/src/mainboard/system76/oryp8/cmos.default new file mode 100644 index 0000000..06b0433 --- /dev/null +++ b/src/mainboard/system76/oryp8/cmos.default @@ -0,0 +1,2 @@ +boot_option=Fallback +debug_level=Debug diff --git a/src/mainboard/system76/oryp8/cmos.layout b/src/mainboard/system76/oryp8/cmos.layout new file mode 100644 index 0000000..ac81752 --- /dev/null +++ b/src/mainboard/system76/oryp8/cmos.layout @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +984 16 h 0 check_sum + +enumerations + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 983 984 diff --git a/src/mainboard/system76/oryp8/data.vbt b/src/mainboard/system76/oryp8/data.vbt new file mode 100644 index 0000000..5641c17 --- /dev/null +++ b/src/mainboard/system76/oryp8/data.vbt Binary files differ diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb new file mode 100644 index 0000000..cd2e617 --- /dev/null +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -0,0 +1,221 @@ +chip soc/intel/tigerlake + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# CPU (soc/intel/tigerlake/cpu.c) + # Power limits + register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 90, + }" + register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 90, + }" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + # Enable C6 DRAM + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SLEW_FAST_8" + register "FastPkgCRampDisable" = "1" + + # FIVR configuration + # Read EXT_RAIL_CONFIG to determine bitmaps + # sudo devmem2 0xfe0011b8 + # 0x0 + # Read EXT_V1P05_VR_CONFIG + # sudo devmem2 0xfe0011c0 + # 0x1a42000 + # Read EXT_VNN_VR_CONFIG0 + # sudo devmem2 0xfe0011c4 + # 0x1a42000 + # TODO: v1p05 voltage and vnn icc max? + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = 0, + .vnn_enable_bitmap = 0, + .v1p05_supported_voltage_bitmap = 0, + .vnn_supported_voltage_bitmap = 0, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1050, + }" + + # Read LPM_EN, make sure to invert the bits + # sudo devmem2 0xfe001c78 + # 0x9 + register "LpmStateDisableMask" = " + LPM_S0i2_1 | + LPM_S0i2_2 | + LPM_S0i3_1 | + LPM_S0i3_2 | + LPM_S0i3_3 | + LPM_S0i3_4 + " + + # Thermal + register "tcc_offset" = "10" + + # Enable CNVi BT + register "CnviBtCore" = "true" + +# PM Util (soc/intel/tigerlake/pmutil.c) + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_R" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_D" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + subsystemid 0x1558 0x65f1 inherit + + #From CPU EDS(575683) + device ref system_agent on end + device ref peg1 on + # PCIe PEG1 x16, Clock 9 (DGPU) + register "PcieClkSrcUsage[9]" = "0x41" + register "PcieClkSrcClkReq[9]" = "9" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH + register "enable_delay_ms" = "16" + register "enable_off_delay_ms" = "4" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "4" + # TODO: Support disable/enable CPU RP clock + register "srcclk_pin" = "-1" # PEG_CLKREQ# + device generic 0 on end + end + end + device ref igpu on + # DDIA is eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + end + device ref dptf on + register "Device4Enable" = "1" + end + device ref peg0 on + # PCIe PEG0 x4, Clock 7 (SSD1) + register "PcieClkSrcUsage[7]" = "0x40" + register "PcieClkSrcClkReq[7]" = "7" + end + device ref tbt_pcie_rp0 on end # TYPEC1 + device ref gna on end + device ref north_xhci on # TYPEC1 + register "TcssXhciEn" = "1" + end + device ref tbt_dma0 on end # TYPEC1 + + # From PCH EDS(615985) + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 1) + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 2) + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 1) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 2) + end + device ref shared_ram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""SYNA1202"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_R12)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref heci1 on end + device ref uart2 on + # Debug console + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref sata on + register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A) + end + device ref pcie_rp5 on + # PCIe root port #5 x1, Clock 8 (GLAN) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[8]" = "4" + register "PcieClkSrcClkReq[8]" = "8" + end + device ref pcie_rp6 on + # PCIe root port #6 x1, Clock 10 (CARD) + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[10]" = "5" + register "PcieClkSrcClkReq[10]" = "10" + end + device ref pcie_rp8 on + # PCIe root port #8 x1, Clock 2 (WLAN) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[2]" = "7" + register "PcieClkSrcClkReq[2]" = "2" + end + device ref pcie_rp9 on + # PCIe root port #9 x4, Clock 6 (SSD2) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[6]" = "8" + register "PcieClkSrcClkReq[6]" = "6" + end + device ref pch_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0E01" # AP/EC command + register "gen3_dec" = "0x00fc0F01" # AP/EC debug + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref pmc hidden end + device ref hda on + register "PchHdaAudioLinkHdaEnable" = "1" + end + device ref smbus on + register "SmbusEnable" = "1" + chip drivers/i2c/tas5825m + register "id" = "0" + device i2c 4e on end # (8bit address: 0x9c) + end + end + device ref fast_spi on end + end +end diff --git a/src/mainboard/system76/oryp8/dsdt.asl b/src/mainboard/system76/oryp8/dsdt.asl new file mode 100644 index 0000000..fb40a5d --- /dev/null +++ b/src/mainboard/system76/oryp8/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/tigerlake/acpi/tcss.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/oryp8/gpio.c b/src/mainboard/system76/oryp8/gpio.c new file mode 100644 index 0000000..80ab6c4 --- /dev/null +++ b/src/mainboard/system76/oryp8/gpio.c @@ -0,0 +1,281 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7 + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_NC(GPD11, NONE), + PAD_NC(GPD12, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS#_EC + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_NC(GPP_A9, NONE), + PAD_CFG_GPI(GPP_A10, UP_20K, DEEP), // SERIRQ_ESPI_ALERT0 + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_B1, NONE, DEEP), // VRALERT#_PD + PAD_CFG_GPI(GPP_B2, NONE, DEEP), + PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ2# + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_CFG_GPO(GPP_B15, 1, DEEP), // SATA_M2_PWR_EN1 + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT strap + PAD_CFG_GPI(GPP_B23, NONE, DEEP), // CPUNSSC clock + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT + PAD_CFG_GPI(GPP_C2, NONE, DEEP), // CNVI_WAKE# + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // PCH_I2C_SDA + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // PCH_I2C_SCL + PAD_CFG_GPI(GPP_C5, NONE, DEEP), // eSPI/LPC select strap + PAD_CFG_GPI(GPP_C6, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_C7, NONE, DEEP), // SWI# + PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET + PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPI(GPP_C11, NONE, DEEP), // BOARD_ID3 + PAD_CFG_GPI(GPP_C12, NONE, DEEP), // BOARD_ID4 + PAD_NC(GPP_C13, NONE), + PAD_CFG_GPI(GPP_C14, NONE, DEEP), // GPP_C14_RTD3 + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // I2C_SDA_Pantone + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // I2C_SCL_Pantone + //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_C22, 0, DEEP), // ROM_I2C_EN + PAD_CFG_GPI(GPP_C23, NONE, DEEP), // SMI# + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), // SML1CLK + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2), // CNVI_RF_RST# + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // SML0_DATA + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), // SML1_DATA + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_CFG_GPO(GPP_D23, 1, DEEP), // GPU_EVENT# + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // M.2_SSD1_PEDET + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI# + PAD_NC(GPP_E4, NONE), + PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), // M2_P1_SATA_DEVSLP + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# + PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# + PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3# + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2), + PAD_CFG_GPO(GPP_F1, 1, DEEP), // LAN_PLT_RST# + PAD_CFG_GPO(GPP_F2, 1, PLTRST), // GPIO_LANRTD3 + PAD_CFG_GPO(GPP_F3, 0, PLTRST), // GPP_F3_TBT_FORCE_PWR + PAD_CFG_GPO(GPP_F4, 1, DEEP), // SATA_PWR_EN + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F6, 1, DEEP), // GPIO_LAN_EN + PAD_CFG_GPO(GPP_F7, 0, DEEP), // PCH_GPIO_PK_MUTE + //PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH + //PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPO(GPP_F17, 1, DEEP), // SB_BLON + PAD_CFG_GPO(GPP_F18, 1, DEEP), // EAPD_MODE + //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + PAD_NC(GPP_F22, NONE), // PCH_VNN_CTRL + PAD_CFG_GPO(GPP_F23, 1, PLTRST), // CARD_RTD3_RST# + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_CFG_GPO(GPP_G6, 1, DEEP), // GPIO_CARD_AUX + PAD_CFG_GPO(GPP_G7, 1, DEEP), // GPIO_CARD + PAD_NC(GPP_G8, NONE), + PAD_CFG_GPI(GPP_G9, NONE, DEEP), // GPP_G9 + PAD_NC(GPP_G10, NONE), + PAD_CFG_GPI(GPP_G11, NONE, DEEP), // GPP_G11 + PAD_NC(GPP_G12, NATIVE), // GPP_G12_TBT_LSX_TXD + PAD_NC(GPP_G13, NATIVE), // GPP_G13_TBT_LSX0_RXD + PAD_NC(GPP_G14, NONE), + PAD_CFG_GPI(GPP_G15, NONE, DEEP), // GPP_G15 + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // SSD_CLKREQ6# + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SDD_PEX4_CLKREQ7# + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // LAN_CLKREQ8# + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // PEG_CLKREQ9# + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // CARD_CLKREQ10# + PAD_NC(GPP_H5, NONE), + PAD_CFG_GPI(GPP_H6, NONE, DEEP), // SB_KBCRST# + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_GPI(GPP_H10, NONE, DEEP), // SML2CLK + PAD_CFG_GPI(GPP_H11, NONE, DEEP), // SML2DATA + PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H12 + PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML3CLK + PAD_CFG_GPI(GPP_H14, NONE, DEEP), // SML3DATA + PAD_CFG_GPI(GPP_H15, NONE, PLTRST), // SML3ALERT# + PAD_CFG_GPI(GPP_H16, NONE, DEEP), // SML4CLK + PAD_CFG_GPO(GPP_H17, 1, DEEP), // SATA_M2_PWR_EN2 + PAD_CFG_GPI(GPP_H18, NONE, DEEP), // GPP_H18 + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_CFG_GPO(GPP_H23, 1, DEEP), // GPP_H23_SDD1_RST# + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT + _PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // G_DP_DHPD_E + _PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // CPU_DPIP0_HPD + PAD_NC(GPP_I4, NONE), + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_CFG_GPO(GPP_I9, 1, DEEP), // GGPP_I9_SDD2_RST# + PAD_NC(GPP_I10, NONE), + PAD_CFG_GPI(GPP_I11, NONE, PLTRST), // USB_OC4# + PAD_CFG_GPI(GPP_I12, NONE, PLTRST), // USB_OC5# + PAD_CFG_GPI(GPP_I13, NONE, PLTRST), // USB_OC6# + PAD_CFG_GPI(GPP_I14, NONE, PLTRST), // USB_OC7# + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // GPP_J1 + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J8, NONE, PLTRST), // GPIO4_NVDD_EN + PAD_NC(GPP_J9, NONE), + + /* ------- GPIO Group GPP_K ------- */ + PAD_CFG_GPO(GPP_K0, 0, DEEP), // OVRM + PAD_NC(GPP_K1, NONE), + PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R + PAD_NC(GPP_K3, NONE), + PAD_NC(GPP_K4, NONE), + PAD_NC(GPP_K5, NONE), + PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1), // SB_IEDP_HPD + PAD_NC(GPP_K7, NONE), + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + PAD_NC(GPP_K10, NONE), + PAD_CFG_GPI(GPP_K11, NONE, PLTRST), // GC6_FB_EN_PCH + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // CHIP_ID1 + PAD_CFG_GPI(GPP_R9, NONE, DEEP), // GSYNC_DET + PAD_CFG_GPI(GPP_R10, NONE, DEEP), // DDS_DET + PAD_CFG_GPI(GPP_R11, NONE, DEEP), // CHIP_ID0 + PAD_CFG_GPI_INT(GPP_R12, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_NC(GPP_R13, NONE), + PAD_NC(GPP_R14, NONE), + PAD_NC(GPP_R15, NONE), + PAD_CFG_GPI(GPP_R16, NONE, DEEP), // BL_PWM_EN_EC + PAD_CFG_GPI(GPP_R17, NONE, DEEP), // PLVDD_RST_EC + PAD_CFG_GPI(GPP_R18, NONE, DEEP), // MUX_CTRL_BIOS + PAD_CFG_GPI(GPP_R19, NONE, DEEP), // PS8461_SW + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_CFG_GPI(GPP_S6, NONE, DEEP), // DMIC_CLK0 + PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DATA0 +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/oryp8/gpio_early.c b/src/mainboard/system76/oryp8/gpio_early.c new file mode 100644 index 0000000..1cc1267 --- /dev/null +++ b/src/mainboard/system76/oryp8/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/oryp8/hda_verb.c b/src/mainboard/system76/oryp8/hda_verb.c new file mode 100644 index 0000000..47d28dd --- /dev/null +++ b/src/mainboard/system76/oryp8/hda_verb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x155865f1, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155865f1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x04451150), +}; + +const u32 pc_beep_verbs[] = { + // Enable DMIC microphone on ALC1220 + 0x02050036, + 0x02042a6a, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/oryp8/include/mainboard/gpio.h b/src/mainboard/system76/oryp8/include/mainboard/gpio.h new file mode 100644 index 0000000..c6393be --- /dev/null +++ b/src/mainboard/system76/oryp8/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/oryp8/ramstage.c b/src/mainboard/system76/oryp8/ramstage.c new file mode 100644 index 0000000..a3a83a8 --- /dev/null +++ b/src/mainboard/system76/oryp8/ramstage.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // PEG0 Config + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // PEG1 Config + params->CpuPcieRpAdvancedErrorReporting[1] = 0; + params->CpuPcieRpLtrEnable[1] = 1; + params->CpuPcieRpPtmEnabled[1] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[8] = 1; // TYPEC1 + params->UsbTcPortEn = 1; + + // Low latency legacy I/O + params->PchLegacyIoLowLatency = 1; + + mainboard_configure_gpios(); +} diff --git a/src/mainboard/system76/oryp8/romstage.c b/src/mainboard/system76/oryp8/romstage.c new file mode 100644 index 0000000..affe636 --- /dev/null +++ b/src/mainboard/system76/oryp8/romstage.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/util.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +static const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + .ddr4_config = { + .dq_pins_interleaved = true, + }, +}; + +static const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const bool half_populated = false; + + // Enable M.2 PCIE 4.0 and PEG1 + mupd->FspmConfig.CpuPcieRpEnableMask = 0x3; + + memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/oryp8/tas5825m.c b/src/mainboard/system76/oryp8/tas5825m.c new file mode 100644 index 0000000..d2f829f --- /dev/null +++ b/src/mainboard/system76/oryp8/tas5825m.c @@ -0,0 +1,1787 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <drivers/i2c/tas5825m/tas5825m.h> + +static int program_dsp_ram(struct device *dev) +{ + int res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, + 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, + 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, + 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, + 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, + 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, + 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xFC, 0x00, 0x00, 0x00, 0x82, 0x00, 0x93, 0x00, + 0xFC, 0x00, 0x00, 0x8F, 0x00, 0xFF, 0xEF, 0x84, + 0x49, 0x03, 0x27, 0x84, 0x02, 0x04, 0x06, 0x02, + 0x60, 0x00, 0x01 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x01, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, + 0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, + 0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, + 0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, + 0x31, 0xA8, 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, + 0xF1, 0xC3, 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, + 0x03, 0x27, 0x02, 0x70, 0x00, 0x04, 0x84 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x41, 0x03, 0x37, 0x80, 0x07, 0x00, 0x80, 0xE0, + 0x00, 0x11, 0xA9, 0x84, 0x82, 0x00, 0xE0, 0x8E, + 0xFC, 0x04, 0x10, 0xF0, 0x1C, 0x11, 0xAA, 0xF0, + 0x1C, 0x11, 0xAB + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x20, 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, + 0x30, 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, + 0xE0, 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, + 0xB3, 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x51, 0xB5, 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, + 0x51, 0xB7, 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, + 0x80, 0xEA, 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, + 0x04, 0x05, 0x84, 0x51, 0x03, 0x75, 0xE2 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x6B, 0xC0, 0x00, 0x80, 0x07, 0x00, 0x80, 0xE0, + 0x80, 0x31, 0xB8, 0x84, 0x82, 0x40, 0xE0, 0xF0, + 0x1C, 0x51, 0xB9, 0xF0, 0x1C, 0x51, 0xBA, 0xF0, + 0x1C, 0x51, 0xBB + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x20, 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, + 0x4A, 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, + 0x48, 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, + 0x32, 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, + 0x40, 0xE0, 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, + 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, + 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, 0x84 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xD3, 0x03, 0x4F, 0xF0, 0x1C, 0x51, 0xBE, 0xF0, + 0x1C, 0x51, 0xBF, 0xF0, 0x1C, 0x51, 0xC0, 0xF0, + 0x1F, 0x51, 0xC1, 0x84, 0xA1, 0x03, 0x65, 0x80, + 0x27, 0x80, 0xEA + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, + 0x7F, 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, + 0x11, 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, + 0xC4, 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, + 0x04, 0x01, 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, + 0x50, 0x01, 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, + 0xC4, 0x04, 0x8F, 0x30, 0x00, 0x00, 0x88 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x67, 0x03, 0x00, 0xE4, 0x00, 0x11, 0x9B, 0xEE, + 0x64, 0x60, 0x00, 0x02, 0xD3, 0x00, 0x10, 0x88, + 0x47, 0x00, 0x80, 0x10, 0x00, 0x18, 0x02, 0x86, + 0xC1, 0x01, 0x9D + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x04, 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, + 0x67, 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, + 0x02, 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, + 0x30, 0x02, 0x78, 0x00, 0x03, 0x02, 0x68 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, + 0x06, 0x12, 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, + 0x71, 0xA9, 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, + 0x00, 0xE0, 0x84, 0x2A, 0x04, 0x00, 0xF0 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, 0xF0, + 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, 0x86, + 0xA1, 0x01, 0xAE, 0x80, 0x27, 0x80, 0xE8, 0x84, + 0x82, 0x04, 0x07 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x05, 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, + 0x08, 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, + 0x6D, 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, + 0x82, 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x12, 0xBC, 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, + 0xA0, 0x00, 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, + 0x20, 0xE0, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, + 0x31, 0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x1F, 0x31, 0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80, + 0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4, + 0x1D, 0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4, + 0x1F, 0x31, 0xA8 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xA9, 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, + 0x10, 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, + 0xAB, 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, + 0xAD, 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x80, 0xEB, 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, + 0x03, 0x3D, 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, + 0x10, 0x20, 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, + 0x26, 0x30, 0x84, 0xC3, 0x03, 0x57, 0x84 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xC2, 0x60, 0xE0, 0xE0, 0x10, 0x11, 0xB3, 0xF0, + 0x1C, 0x71, 0xB4, 0xF0, 0x1C, 0x71, 0xB5, 0xF0, + 0x1C, 0x71, 0xB6, 0xF0, 0x1F, 0x71, 0xB7, 0x86, + 0xA1, 0x01, 0xC6 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xE0, 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, + 0xBA, 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, + 0xBC, 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, + 0xE8, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x81, 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, + 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, + 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, + 0x03, 0x76, 0x08, 0x00, 0x30, 0x48, 0x02 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, 0x84, + 0x41, 0x03, 0x46, 0xE4, 0x10, 0x40, 0x00, 0x80, + 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x00, 0xE0, 0x84, + 0xC3, 0x03, 0x5F + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xC0, 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, + 0x66, 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, + 0x00, 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, + 0x6B, 0x08, 0x00, 0x30, 0x68, 0x84, 0x43 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x03, 0x46, 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, + 0x03, 0x26, 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, + 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, + 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, 0x8C + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xFF, 0x03, 0x24, 0x84, 0xCB, 0x03, 0x66, 0xE0, + 0x10, 0x51, 0xC4, 0x84, 0x80, 0x41, 0x00, 0x02, + 0xA3, 0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84, + 0xD0, 0x04, 0x09 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, + 0x80, 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, + 0x9D, 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, + 0x9E, 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x01, 0x9C, 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, + 0x00, 0x00, 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, + 0x00, 0x01, 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, + 0x00, 0x02, 0x84, 0x49, 0x03, 0x6E, 0x84 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x41, 0x03, 0x6F, 0x84, 0xC8, 0x04, 0x10, 0x84, + 0xC0, 0x04, 0x0A, 0x04, 0x81, 0x91, 0x20, 0x08, + 0x60, 0x26, 0x30, 0x0D, 0x00, 0x10, 0x10, 0x08, + 0x60, 0x06, 0x12 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xAE, 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, + 0x0E, 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, + 0xE8, 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, + 0xAF, 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x11, 0xB1, 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, + 0x00, 0x1A, 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, + 0x04, 0x0F, 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, + 0xE0, 0x80, 0x84, 0x43, 0x03, 0x6F, 0x80 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x07, 0x12, 0xBD, 0x02, 0xC0, 0x00, 0x00, 0x00, + 0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x11, 0x8F, + 0x00, 0xFF, 0xFF, 0x84, 0x58, 0x04, 0x01, 0x84, + 0xC2, 0x04, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x50, 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, + 0x00, 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, + 0x00, 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, + 0x1E, 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x26, 0x33, 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, + 0x40, 0x83, 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, + 0x61, 0x00, 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, + 0x2C, 0x09, 0x84, 0xCA, 0x21, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x01 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + return 0; +} + +static int program_biquad_filters(struct device *dev) +{ + int res; + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x10, 0x92, 0xFE, 0xF0, 0x84, 0x2F, 0xC0, + 0x07, 0x6F, 0x67, 0x29, 0x0F, 0x7B, 0xD0, 0x40, + 0xF8, 0x80, 0x05, 0xDA, 0x08, 0x18, 0xBA, 0xDB, + 0xF0, 0xA9, 0xF7, 0x0B, 0x07, 0x44, 0x20 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x4E, 0x0F, 0x56, 0x08, 0xF5, 0xF8, 0xA3, 0x24, + 0xD7, 0x08, 0x20, 0x24, 0xC9, 0xF1, 0x08, 0x6D, + 0x45, 0x06, 0xE7, 0x92, 0x27, 0x0E, 0xF7, 0x92, + 0xBB, 0xF8, 0xF8, 0x49, 0x10, 0x08, 0x13 + }; + res = tas5825m_write_block_at(dev, 0x4F, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xEA, 0xAD, 0xF3, 0x14, 0xE9, 0xB1, 0x05, 0x4B, + 0xD4, 0xF4, 0x0C, 0xEB, 0x16, 0x4F, 0xFA, 0xA0, + 0x40, 0x5F + }; + res = tas5825m_write_block_at(dev, 0x6E, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x13, 0x8A, 0xBF, 0xF0, 0x78, 0x40, 0xD7, + 0x07, 0x77, 0x45, 0xB3, 0x0F, 0x87, 0xBF, 0x29, + 0xF8, 0x75, 0x2F, 0x8E, 0x08, 0x46, 0x76, 0x67, + 0xF6, 0x0C, 0xF9, 0x7A, 0x03, 0x36, 0x96 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xD5, 0x09, 0xF3, 0x06, 0x86, 0xFC, 0x82, 0xF2, + 0xC4, 0x08, 0x0B, 0x02, 0xAF, 0xF0, 0xBC, 0xDB, + 0x13, 0x07, 0x40, 0x84, 0x68, 0x0F, 0x43, 0x24, + 0xED, 0xF8, 0xB4, 0x78, 0xEA, 0x08, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xB7, 0x9B, 0x16, + 0xF0, 0x90, 0xC9, 0xD5, 0x07, 0xB7, 0x9B + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x16, 0x0F, 0x6D, 0xB0, 0xA9, 0xF8, 0x8F, 0x44, + 0x52, 0x07, 0xBB, 0x6D, 0x71, 0xF0, 0xCF, 0x04, + 0xEA, 0x07, 0x7F, 0x86, 0x4C, 0x0F, 0x30, 0xFB, + 0x16, 0xF8, 0xC5, 0x0C, 0x43, 0x08, 0x49 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x93, 0xE5, 0xF0, 0x43, 0x4D, 0x1F, 0x07, 0x7D, + 0x73, 0x57, 0x0F, 0xC0, 0x4F, 0x67, 0xF8, 0x3C, + 0x95, 0x49, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xB7, 0x9B, 0x16, 0xF0, 0x90, + 0xC9, 0xD5, 0x07, 0xB7, 0x9B, 0x16, 0x0F + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x6D, 0xB0, 0xA9, 0xF8, 0x8F, 0x44, 0x52, 0x07, + 0xBB, 0x6D, 0x71, 0xF0, 0xCF, 0x04, 0xEA, 0x07, + 0x7F, 0x86, 0x4C, 0x0F, 0x30, 0xFB, 0x16, 0xF8, + 0xC5, 0x0C, 0x43 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x49, 0x93, 0xE5, 0xF0, 0x43, 0x4D, 0x1F, + 0x07, 0x7D, 0x73, 0x57, 0x0F, 0xC0, 0x4F, 0x67, + 0xF8, 0x3C, 0x95, 0x49, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x99, 0xF7, 0x27, 0xFF, 0x09, 0x5A, 0xB9, + 0x00, 0x66, 0xFF, 0x35, 0x0F, 0xB7, 0xB4, 0x87, + 0xF8, 0x3D, 0xFA, 0x65 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3D, 0x95, + 0xFF, 0xFE, 0x7B, 0x29, 0xFF, 0xFF, 0x3D + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x95, 0x0F, 0x62, 0x3F, 0x77, 0xF8, 0x9A, 0xB6, + 0xDB, 0x07, 0xB1, 0xE2, 0x27, 0xF0, 0x9C, 0x3B, + 0xB2, 0x07, 0xB1, 0xE2, 0x27, 0x0F, 0x62, 0x3F, + 0x77, 0xF8, 0x9A, 0xB6, 0xDB, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x38, 0xE4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, + 0x71, 0xC7 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + return 0; +} + +int tas5825m_setup(struct device *dev, int id) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x63, 0x03); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x64, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + // Set to HiZ state and enable DSP + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + // Digital core and registers reset + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x7C); + if (res < 0) + return res; + + // Reset to HiZ state and enable DSP + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + // Wait for device to settle + mdelay(5); + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + // DSP reset + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + // Program DSP RAM + res = program_dsp_ram(dev); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5B, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x7A, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xC1, 0xF8, 0x59, 0x7F, 0x63 + }; + res = tas5825m_write_block_at(dev, 0x7B, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0xE9, 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, + 0x54, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, + 0x48, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, + 0x76, 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04 + }; + res = tas5825m_write_block_at(dev, 0x27, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, + 0x98, 0xC8, 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x46, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, + 0xBB, 0x98, 0xC8 + }; + res = tas5825m_write_block_at(dev, 0x65, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x37, 0xDF, 0xC0, + 0x00, 0x37, 0xDF, 0xC0, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0x60, 0x3F, 0x2A, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x1A, 0xB4, 0xF9, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + // Program biquad filters + res = program_biquad_filters(dev); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + // Register tuning + res = tas5825m_write_at(dev, 0x60, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x63, 0x03); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x30); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x0B); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + // Clear analog fault + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + mdelay(100); + + // Set to PLAY state + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/57652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb Gerrit-Change-Number: 57652 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/system76/oryp8: Add System76 Oryx Pro 8
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57652 ) Change subject: mb/system76/oryp8: Add System76 Oryx Pro 8 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb Gerrit-Change-Number: 57652 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 20:48:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/system76/bonw14: Add System76 Bonobo Workstation 14
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49173 ) Change subject: mb/system76/bonw14: Add System76 Bonobo Workstation 14 ...................................................................... mb/system76/bonw14: Add System76 Bonobo Workstation 14 Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49173 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/bonw14.md A src/mainboard/system76/bonw14/Kconfig A src/mainboard/system76/bonw14/Kconfig.name A src/mainboard/system76/bonw14/Makefile.inc A src/mainboard/system76/bonw14/acpi/dgpu.asl A src/mainboard/system76/bonw14/acpi/gpe.asl A src/mainboard/system76/bonw14/acpi/mainboard.asl A src/mainboard/system76/bonw14/acpi/sleep.asl A src/mainboard/system76/bonw14/board_info.txt A src/mainboard/system76/bonw14/bootblock.c A src/mainboard/system76/bonw14/cmos.default A src/mainboard/system76/bonw14/cmos.layout A src/mainboard/system76/bonw14/devicetree.cb A src/mainboard/system76/bonw14/dsdt.asl A src/mainboard/system76/bonw14/gpio.c A src/mainboard/system76/bonw14/gpio_early.c A src/mainboard/system76/bonw14/hda_verb.c A src/mainboard/system76/bonw14/include/mainboard/gpio.h A src/mainboard/system76/bonw14/ramstage.c A src/mainboard/system76/bonw14/romstage.c 21 files changed, 982 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 28c500a..77af473 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -182,6 +182,7 @@ - [Adder Workstation 1](system76/addw1.md) - [Adder Workstation 2](system76/addw2.md) +- [Bonobo Workstation 14](system76/bonw14.md) - [Darter Pro 6](system76/darp6.md) - [Darter Pro 7](system76/darp7.md) - [Galago Pro 4](system76/galp4.md) diff --git a/Documentation/mainboard/system76/bonw14.md b/Documentation/mainboard/system76/bonw14.md new file mode 100644 index 0000000..2ea866b --- /dev/null +++ b/Documentation/mainboard/system76/bonw14.md @@ -0,0 +1,77 @@ +# System76 Bonobo Workstation 14 (bonw14) + +## Specs + +- CPU + - Intel Core i5-10600K + - Intel Core i7-10700K + - Intel Core i9-10900K +- Chipset + - Intel Z490 +- EC + - ITE IT5570E running [System76 EC](https://github.com/system76/ec) +- Grahpics + - dGPU options + - NVIDIA GeForce RTX 2080 Super + - NVIDIA GeForce RTX 2070 Super + - NVIDIA GeForce RTX 2060 + - eDP options + - 17.3" 1920x1080x144Hz LCD (LG LP173WFG-SPB1) + - 17.3" 3840x2160@60Hz LCD (AUO B173ZAN03.0) + - 1x HDMI + - 2x Mini DisplayPort 1.4 + - 2x DisplayPort 1.4 over USB-C +- Memory + - Up to 128GB (4x32GB) quad-channel DDR4 SO-DIMMs @ 3200 MHz +- Networking + - Gigabit Ethernet + - M.2 PCIe/CNVi WiFi/Bluetooth + - Intel Wi-Fi 6 AX200/AX201 +- Power + - 2x 280W (20V 14A) AC barrel adapter + - Chicony A18-280P1A, using a C13 power cord + - 97Wh 8-cell Lithium-Ion battery +- Sound + - Realtek ALC1220 codec + - 2x TI TAS5825MRHBR smart AMPs + - Internal speakers (stereo + subwoofer) and microphone + - Combined 3.5mm headphone/microphone jack + - Combined 3.5mm microphone and S/PDIF jack + - HDMI, Mini DisplayPort, USB-C DisplayPort audio +- Storage + - 2x M.2 PCIe NVMe or SATA SSD + - 1x M.2 PCIe NVMe-only SSD + - 1x M.2 SATA-only SSD + - SD card reader (RTS5260) +- USB + - 1x USB Type-C with Thunderbolt 3 + - 1x USB 3.2 Gen 2 Type-C with DisplayPort 1.4 + - 1x USB 3.2 Gen 2x2 Type-C + - 3x USB 3.2 Gen 2 Type-A +- Dimensions + - 4.343cm x 39.903cm x 31.902cm, 3.80kg + +## Flashing coreboot + +```eval_rst ++---------------------+---------------------+ +| Type | Value | ++=====================+=====================+ +| Socketed flash | no | ++---------------------+---------------------+ +| Vendor | GigaDevice | ++---------------------+---------------------+ +| Model | GD25B127D | ++---------------------+---------------------+ +| Size | 16 MiB | ++---------------------+---------------------+ +| Package | SOIC-8 | ++---------------------+---------------------+ +| Internal flashing | yes | ++---------------------+---------------------+ +| External flashing | yes | ++---------------------+---------------------+ +``` + +External flashing via ISP requires removing the board from the chassis. +The flash chip (U16) is next to the PCH. diff --git a/src/mainboard/system76/bonw14/Kconfig b/src/mainboard/system76/bonw14/Kconfig new file mode 100644 index 0000000..6f93e09 --- /dev/null +++ b/src/mainboard/system76/bonw14/Kconfig @@ -0,0 +1,56 @@ +if BOARD_SYSTEM76_BONW14 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_BAT_THRESHOLDS + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_HOTPLUG + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COMETLAKE_S + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_RDRESP_NEED_DELAY + +config MAINBOARD_DIR + default "system76/bonw14" + +config MAINBOARD_PART_NUMBER + default "bonw14" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Bonobo WS" + +config MAINBOARD_VERSION + default "bonw14" + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config UART_FOR_CONSOLE + default 2 + +config MAX_CPUS + default 20 + +config DIMM_MAX + default 4 + +config POST_DEVICE + default n + +endif diff --git a/src/mainboard/system76/bonw14/Kconfig.name b/src/mainboard/system76/bonw14/Kconfig.name new file mode 100644 index 0000000..982a9cb --- /dev/null +++ b/src/mainboard/system76/bonw14/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SYSTEM76_BONW14 + bool "bonw14" diff --git a/src/mainboard/system76/bonw14/Makefile.inc b/src/mainboard/system76/bonw14/Makefile.inc new file mode 100644 index 0000000..a866021 --- /dev/null +++ b/src/mainboard/system76/bonw14/Makefile.inc @@ -0,0 +1,10 @@ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/system76/bonw14/acpi/dgpu.asl b/src/mainboard/system76/bonw14/acpi/dgpu.asl new file mode 100644 index 0000000..6521ee9 --- /dev/null +++ b/src/mainboard/system76/bonw14/acpi/dgpu.asl @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (\_SB.PCI0.PEG0) +{ + Name (_ADR, 0x00010000) + + Device (PEGP) + { + Name (_ADR, 0) + + // Convert a byte to a hex string, trimming extra parts + Method (BHEX, 1) + { + Local0 = ToHexString(Arg0) + Return (Mid(Local0, SizeOf(Local0) - 2, 2)) + } + + // UUID to string + Method (IDST, 1) + { + Local0 = "" + Fprintf( + Local0, + "%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o", + BHEX(DerefOf(Arg0[3])), + BHEX(DerefOf(Arg0[2])), + BHEX(DerefOf(Arg0[1])), + BHEX(DerefOf(Arg0[0])), + BHEX(DerefOf(Arg0[5])), + BHEX(DerefOf(Arg0[4])), + BHEX(DerefOf(Arg0[7])), + BHEX(DerefOf(Arg0[6])), + BHEX(DerefOf(Arg0[8])), + BHEX(DerefOf(Arg0[9])), + BHEX(DerefOf(Arg0[10])), + BHEX(DerefOf(Arg0[11])), + BHEX(DerefOf(Arg0[12])), + BHEX(DerefOf(Arg0[13])), + BHEX(DerefOf(Arg0[14])), + BHEX(DerefOf(Arg0[15])) + ) + Return (Local0) + } + + // Safe hex conversion, checks type first + Method (SFST, 1) + { + Local0 = ObjectType(Arg0) + If (Local0 == 1 || Local0 == 2 || Local0 == 3) { + Return (ToHexString(Arg0)) + } Else { + Return (Concatenate("Type: ", Arg0)) + } + } + + Method (_DSM, 4, Serialized) + { + Debug = "NVIDIA _DSM" + Printf(" Arg0: %o", IDST(Arg0)) + Printf(" Arg1: %o", SFST(Arg1)) + Printf(" Arg2: %o", SFST(Arg2)) + Printf(" Arg3: %o", SFST(Arg3)) + + If (Arg0 == ToUUID ("d4a50b75-65c7-46f7-bfb7-41514cea0244")) { + If (Arg1 != 0x0102) { + Printf(" Invalid Arg1, return 0x80000002") + Return (0x80000002) + } + + If (Arg2 == 0) { + Printf(" Arg2 == 0x00, return supported functions") + Return (Buffer (4) { 0x01, 0x00, 0x10, 0x00 }) + } + + If (Arg2 == 0x14) { + Printf(" Arg2 == 0x14, return backlight package") + Return (Package (9) { + 0x8000A450, + 0x0200, + 0, + 0, + 1, + 1, + 200, + 32, + 1000 + }) + } + + Printf(" Unknown Arg2, return 0x80000002") + Return (0x80000002) + } + + Printf(" Unknown Arg0, return 0x80000001") + Return (0x80000001) + } + + // _DOD: Display Output Devices + Method (_DOD, 0, NotSerialized) + { + Return (Package (3) { + 0x80008320, + 0x80006330, + 0x8000A450 + }) + } + + Device (HDM0) + { + Name (_ADR, 0x80008320) + } + + Device (DSP0) + { + Name (_ADR, 0x80006330) + } + + Device (DSP1) + { + Name (_ADR, 0x8000A450) + } + } +} diff --git a/src/mainboard/system76/bonw14/acpi/gpe.asl b/src/mainboard/system76/bonw14/acpi/gpe.asl new file mode 100644 index 0000000..7ef9a98 --- /dev/null +++ b/src/mainboard/system76/bonw14/acpi/gpe.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// GPP_K6 SCI +Method (_L06, 0, Serialized) { + Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == 1) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/system76/bonw14/acpi/mainboard.asl b/src/mainboard/system76/bonw14/acpi/mainboard.asl new file mode 100644 index 0000000..0a4c64c --- /dev/null +++ b/src/mainboard/system76/bonw14/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x03 /* GPP_K3 */ +#define EC_GPE_SWI 0x06 /* GPP_K6 */ +#include <ec/system76/ec/acpi/ec.asl> + +Scope (\_SB) { + #include "sleep.asl" +} + +Scope (\_GPE) { + #include "gpe.asl" +} + +#include "dgpu.asl" diff --git a/src/mainboard/system76/bonw14/acpi/sleep.asl b/src/mainboard/system76/bonw14/acpi/sleep.asl new file mode 100644 index 0000000..48c50e0 --- /dev/null +++ b/src/mainboard/system76/bonw14/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/system76/bonw14/board_info.txt b/src/mainboard/system76/bonw14/board_info.txt new file mode 100644 index 0000000..6a8b2da --- /dev/null +++ b/src/mainboard/system76/bonw14/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: bonw14 +Category: laptop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/bonw14/bootblock.c b/src/mainboard/system76/bonw14/bootblock.c new file mode 100644 index 0000000..8d06adc --- /dev/null +++ b/src/mainboard/system76/bonw14/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/system76/bonw14/cmos.default b/src/mainboard/system76/bonw14/cmos.default new file mode 100644 index 0000000..06b0433 --- /dev/null +++ b/src/mainboard/system76/bonw14/cmos.default @@ -0,0 +1,2 @@ +boot_option=Fallback +debug_level=Debug diff --git a/src/mainboard/system76/bonw14/cmos.layout b/src/mainboard/system76/bonw14/cmos.layout new file mode 100644 index 0000000..ac81752 --- /dev/null +++ b/src/mainboard/system76/bonw14/cmos.layout @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +984 16 h 0 check_sum + +enumerations + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 983 984 diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb new file mode 100644 index 0000000..612711d --- /dev/null +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -0,0 +1,224 @@ +chip soc/intel/cannonlake + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 125, + .tdp_pl2_override = 160, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console + }" + + # Misc + register "AcousticNoiseMitigation" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "13" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "PMC_GPP_K" + register "gpe0_dw1" = "PMC_GPP_G" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + subsystemid 0x1558 0x7714 inherit + device pci 00.0 on end # Host Bridge + device pci 01.0 on # GPU Port + # PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU) + register "PcieClkSrcUsage[7]" = "0x40" + register "PcieClkSrcClkReq[7]" = "7" + + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end + # TODO: is this enough to disable iGPU? + device pci 02.0 off end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3 + end + device pci 14.2 on end # Shared SRAM + device pci 14.3 on # CNVi wifi + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataPortsEnable[1]" = "1" # SATA1A (SSD) + register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3) + register "SataPortsEnable[4]" = "1" # SATA4 (SSD2) + end + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1b.0 on # PCI Express Port 17 + # PCI Express root port #17 x4, Clock 14 (SSD2) + register "PcieRpEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "1" + register "PcieClkSrcUsage[14]" = "16" + register "PcieClkSrcClkReq[14]" = "14" + end + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 on # PCI Express Port 21 + # PCI Express root port #21 x4, Clock 15 (SSD3) + register "PcieRpEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "1" + register "PcieClkSrcUsage[15]" = "20" + register "PcieClkSrcClkReq[15]" = "15" + end + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1c.0 on # PCI Express Port 1 + # PCI Express root port #1 x4, Clock 6 (Thunderbolt) + register "PcieRpEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED + register "PcieClkSrcClkReq[6]" = "6" + end + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + # PCI Express root port #5 x4, Clock 10 (USB 3.2) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[10]" = "4" + register "PcieClkSrcClkReq[10]" = "10" + end + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 + # PCI Express root port #9 x4, Clock 8 (SSD) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[8]" = "8" + register "PcieClkSrcClkReq[8]" = "8" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 + # PCI Express root port #13 x1, Clock 0 (WLAN) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[0]" = "12" + register "PcieClkSrcClkReq[0]" = "0" + end + device pci 1d.5 on # PCI Express Port 14 + # PCI Express root port #14 x1, Clock 1 (GLAN) + register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" + register "PcieClkSrcUsage[1]" = "13" + register "PcieClkSrcClkReq[1]" = "1" + end + device pci 1d.6 on # PCI Express Port 15 + # PCI Express root port #15 x1, Clock 4 (Card Reader) + register "PcieRpEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "1" + register "PcieClkSrcUsage[4]" = "14" + register "PcieClkSrcClkReq[4]" = "4" + end + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0e01" + register "gen3_dec" = "0x00fc0f01" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/system76/bonw14/dsdt.asl b/src/mainboard/system76/bonw14/dsdt.asl new file mode 100644 index 0000000..a48382b --- /dev/null +++ b/src/mainboard/system76/bonw14/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/bonw14/gpio.c b/src/mainboard/system76/bonw14/gpio.c new file mode 100644 index 0000000..a80aa14 --- /dev/null +++ b/src/mainboard/system76/bonw14/gpio.c @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // BATLOW_N + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT + PAD_CFG_GPI(GPD2, NATIVE, PWROK), // PCH_LAN_WAKE# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH + PAD_NC(GPD6, UP_20K), + PAD_CFG_GPI(GPD7, UP_20K, PWROK), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_CFG_GPI(GPD11, UP_20K, PWROK), // LANPHYPC + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0 + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1 + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2 + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // 10k pull up + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC + PAD_NC(GPP_A10, UP_20K), + _PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), // INTP_OUT + PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), // 10k pull up + PAD_CFG_GPI(GPP_A13, UP_20K, DEEP), // SUS_PWR_ACK + PAD_NC(GPP_A14, UP_20K), + PAD_CFG_GPI(GPP_A15, UP_20K, DEEP), // SUSACK# + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, UP_20K), + PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_A19, UP_20K, DEEP), // XFI_GAIN + PAD_CFG_GPO(GPP_A20, 1, DEEP), // GPP_A20 (MB det) + PAD_NC(GPP_A21, UP_20K), + PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), // GPP_A22 (MB det) + PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPP_A23 (MB det) + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_B1, UP_20K), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // BT_UART_WAKE_N + PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN + PAD_NC(GPP_B4, UP_20K), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GLAN_CLKREQ# + PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST), // GPIO_CR_RESET_R + PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), // CR_GPIO_WAKE_N_R + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // CR_CLKREQ# + PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST), // PRSNT# + PAD_CFG_GPO(GPP_B11, 1, DEEP), // PCIE_GLAN_RESET + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR + PAD_NC(GPP_B15, UP_20K), + PAD_NC(GPP_B16, UP_20K), + PAD_CFG_GPI(GPP_B17, UP_20K, DEEP), // LPSS_GSPI0_MISO + PAD_CFG_GPI(GPP_B18, UP_20K, DEEP), // LPSS_GSPI0_MOSI + PAD_NC(GPP_B19, UP_20K), + _PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000), // SMI#_3242 + PAD_NC(GPP_B21, UP_20K), + PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // EXI BOOT STALL STRAP + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // TLS CONFIDENTIALITY STRAP + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SMLINK0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SMLINK0_DATA + PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // ESPI/LPC SELECT STRAP + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SMC_CPU_THERM_R + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SMD_CPU_THERM + PAD_CFG_GPI(GPP_C8, NONE, PLTRST), // TPM_DET# + PAD_CFG_GPI(GPP_C9, NONE, DEEP), // GSYNC_ID + PAD_NC(GPP_C10, DN_20K), + PAD_CFG_GPO(GPP_C11, 1, DEEP), // FW_RST# + PAD_NC(GPP_C12, UP_20K), + PAD_NC(GPP_C13, UP_20K), + PAD_NC(GPP_C14, UP_20K), + PAD_NC(GPP_C15, UP_20K), + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // T_SDA + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // T_SCL + PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411 + PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411 + //PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), // UART2_RXD + //PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), // UART2_TXD + PAD_NC(GPP_C22, UP_20K), + PAD_NC(GPP_C23, UP_20K), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, UP_20K), + PAD_NC(GPP_D1, UP_20K), + PAD_NC(GPP_D2, UP_20K), + PAD_NC(GPP_D3, UP_20K), + PAD_NC(GPP_D4, UP_20K), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUR_CLKREQ0 + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), // M.2_BT_PCMIN + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), // M.2_BT_PCMCLK + PAD_NC(GPP_D9, UP_20K), + PAD_NC(GPP_D10, UP_20K), + PAD_NC(GPP_D11, UP_20K), + PAD_NC(GPP_D12, UP_20K), + PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), // 5825_I2C_DAT + PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), // 5825_I2C_CLK + PAD_NC(GPP_D15, UP_20K), + PAD_NC(GPP_D16, UP_20K), + PAD_NC(GPP_D17, UP_20K), + PAD_NC(GPP_D18, UP_20K), + PAD_NC(GPP_D19, UP_20K), + PAD_NC(GPP_D20, UP_20K), + PAD_NC(GPP_D21, UP_20K), + PAD_NC(GPP_D22, UP_20K), + PAD_NC(GPP_D23, UP_20K), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), // 10k pull up + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_DET_N + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), // VCCIO_0_CTRL + PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // SMI# + PAD_NC(GPP_E4, UP_20K), + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SSD1_SATA_DEVSLP + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // SSD3_SATA_DEVSLP + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED# + PAD_CFG_GPI(GPP_E9, UP_20K, DEEP), // RING OSCILLATOR BYPASS STRAP + PAD_CFG_GPI(GPP_E10, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP + PAD_CFG_GPI(GPP_E11, UP_20K, DEEP), // XTAL INPUT FREQUENCY STRAP + PAD_CFG_GPI(GPP_E12, UP_20K, DEEP), // DFX TEST MODE + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2), // 10k pull up + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_DET_N + PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, RSMRST), // GPP_F2_TBT_RST# + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2), // 10k pull up + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2), // 10k pull up + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD4_SATA_DEVSLP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // SSD2_SATA_DEVSLP + PAD_NC(GPP_F7, UP_20K), + PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), // GPU_PWR_EN# + PAD_NC(GPP_F9, UP_20K), + PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // PCH_CONFIG_JUMPER + PAD_CFG_GPO(GPP_F11, 0, DEEP), // SSD1_PWR_DN# + PAD_CFG_GPI(GPP_F12, UP_20K, DEEP), + PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, UP_20K), + PAD_NC(GPP_F16, UP_20K), + PAD_NC(GPP_F17, UP_20K), + PAD_CFG_GPI(GPP_F18, UP_20K, DEEP), // GPIO_PCIESLOT_RST_R + PAD_NC(GPP_F19, UP_20K), + PAD_NC(GPP_F20, UP_20K), + PAD_NC(GPP_F21, UP_20K), + //PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F23, 0, DEEP), // GC_OFF_EN + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, UP_20K), + PAD_NC(GPP_G1, UP_20K), + PAD_NC(GPP_G2, UP_20K), + PAD_NC(GPP_G3, UP_20K), + PAD_NC(GPP_G4, UP_20K), + PAD_NC(GPP_G5, UP_20K), + PAD_NC(GPP_G6, UP_20K), + PAD_NC(GPP_G7, UP_20K), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // TBT_CLKREQ# + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // MXM_REQ# + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // SSD_CLKREQ# + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // PE_CLKREQ# + PAD_NC(GPP_H5, NONE), + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), // WLAN_GPIO_WAKE_N + PAD_CFG_GPO(GPP_H7, 0, DEEP), // PCIE_SSD2_RESET + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SSD2_CLKREQ# + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SSD3_CLKREQ# + PAD_NC(GPP_H10, NONE), + PAD_CFG_GPO(GPP_H11, 0, DEEP), // SSD3_PWR_DN# + PAD_CFG_GPI(GPP_H12, UP_20K, DEEP), // GPP_H_12 + PAD_NC(GPP_H13, UP_20K), + PAD_NC(GPP_H14, UP_20K), + _PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000), // GPP_H15_TBT_WAKE# + PAD_NC(GPP_H16, UP_20K), + PAD_NC(GPP_H17, UP_20K), + PAD_NC(GPP_H18, UP_20K), + PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), // GPIO_CARD_AUX + PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), // GPIO_CARD + PAD_NC(GPP_H21, UP_20K), + PAD_NC(GPP_H22, UP_20K), + PAD_NC(GPP_H23, UP_20K), + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000), // GPPDPA_I0 + _PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000), // GPPDPB_I1 + _PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000), // DP_F_HPD + PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // 100k pull down + PAD_CFG_GPO(GPP_I5, 0, DEEP), // GPIO_TBT_RESET + PAD_CFG_GPI(GPP_I6, UP_20K, DEEP), // MXM_GPIO0 + PAD_CFG_GPI(GPP_I7, UP_20K, DEEP), // 10k pull up + PAD_CFG_GPI(GPP_I8, UP_20K, DEEP), // GPIO_WIFI_RESET_R + PAD_CFG_GPO(GPP_I9, 1, DEEP), // WLAN_EN + PAD_CFG_GPO(GPP_I10, 0, DEEP), // SSD2_PWR_DN# + PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // H_SKTOCC_N + PAD_CFG_GPO(GPP_I12, 0, DEEP), // PCIE_SSD3_RESET + PAD_CFG_GPO(GPP_I13, 0, DEEP), // PCIE_SSD1_RESET + PAD_NC(GPP_I14, UP_20K), + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // CPI_C10_GATE_N (VCCIO_3P3_PWRGATE) + PAD_NC(GPP_J2, UP_20K), + PAD_NC(GPP_J3, UP_20K), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT_R + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT_R + PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // EDP_OD_EN + PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), + + /* ------- GPIO Group GPP_K ------- */ + PAD_CFG_GPI(GPP_K0, UP_20K, DEEP), // PCH_GPIO_PK_MUTE + PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // PCH_GPIO_WOOFER_MUTE + PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // DGPU_PWRGD + _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI# + PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // GPU_EVENT#_R + PAD_CFG_GPO(GPP_K5, 0, DEEP), // DP_MUX_SW + _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI# + PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // E3100_PWR_EN + PAD_CFG_GPO(GPP_K8, 0, DEEP), // SSD4_PWR_DN# + PAD_CFG_GPI(GPP_K9, UP_20K, DEEP), // TBTA_HRESET + PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // MIC_SENSE_PCH + PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // XFI_SENSE_PCH + _PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT# + PAD_NC(GPP_K13, UP_20K), + PAD_CFG_GPO(GPP_K14, 0, DEEP), // 7411_TEST_R + PAD_NC(GPP_K15, UP_20K), + PAD_CFG_TERM_GPO(GPP_K16, 1, UP_20K, DEEP), // TBT_FORCE_PWR_R + PAD_NC(GPP_K17, UP_20K), + PAD_CFG_GPO(GPP_K18, 1, DEEP), // PCH_MUTE# + PAD_NC(GPP_K19, UP_20K), + PAD_CFG_GPI(GPP_K20, UP_20K, DEEP), // TEST_SETUP_MENU + PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN + //PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN# + PAD_CFG_GPO(GPP_K23, 1, RSMRST), // TBT_RTD3_PWR_EN_R +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/bonw14/gpio_early.c b/src/mainboard/system76/bonw14/gpio_early.c new file mode 100644 index 0000000..42bbe42 --- /dev/null +++ b/src/mainboard/system76/bonw14/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), // UART2_TXD + PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH + PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN# +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/bonw14/hda_verb.c b/src/mainboard/system76/bonw14/hda_verb.c new file mode 100644 index 0000000..00f5fdb --- /dev/null +++ b/src/mainboard/system76/bonw14/hda_verb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x15587714, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15587714), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x40000000), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x4094022d), + AZALIA_PIN_CFG(0, 0x1e, 0x04451120), +}; + +const u32 pc_beep_verbs[] = { + // Enable DMIC microphone on ALC1220 + 0x02050036, + 0x02042a6a, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/bonw14/include/mainboard/gpio.h b/src/mainboard/system76/bonw14/include/mainboard/gpio.h new file mode 100644 index 0000000..c6393be --- /dev/null +++ b/src/mainboard/system76/bonw14/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/bonw14/ramstage.c b/src/mainboard/system76/bonw14/ramstage.c new file mode 100644 index 0000000..43ee54f --- /dev/null +++ b/src/mainboard/system76/bonw14/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <mainboard/gpio.h> + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/system76/bonw14/romstage.c b/src/mainboard/system76/bonw14/romstage.c new file mode 100644 index 0000000..8f1687e --- /dev/null +++ b/src/mainboard/system76/bonw14/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg memcfg = { + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa2}, + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa6}, + }, + .rcomp_resistor = { 121, 75, 100 }, + .rcomp_targets = { 50, 26, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + // Allow memory clocks higher than 2933 MHz + memupd->FspmConfig.SaOcSupport = 1; + + // Set primary display to PCIe graphics + memupd->FspmConfig.PrimaryDisplay = 1; + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/49173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d Gerrit-Change-Number: 49173 Gerrit-PatchSet: 17 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/bonw14: Add System76 Bonobo Workstation 14
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49173 ) Change subject: mb/system76/bonw14: Add System76 Bonobo Workstation 14 ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d Gerrit-Change-Number: 49173 Gerrit-PatchSet: 16 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 02 Nov 2021 20:47:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Set soc name for Stoneyridge
by Matt Papageorge (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Bao Zheng, Marshall Dawson, Zheng Bao, Felix Held. Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58555 ) Change subject: amdfwtool: Set soc name for Stoneyridge ...................................................................... Patch Set 3: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/58555/comment/01a05579_c8a06974 PS3, Line 1588: retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, > Yes. This just keeps behavior unchanged. […] I have checked, allegedly stoney supports EFS. But I do not have a device to test this on. It may be good to try this on an actual stoney device to make sure nothing bad happens -- To view, visit https://review.coreboot.org/c/coreboot/+/58555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Gerrit-Change-Number: 58555 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 20:47:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/releases/4.15: Add more System76 boards
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Tim Crawford, Jason Glenesk. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58868 ) Change subject: Documentation/releases/4.15: Add more System76 boards ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0353b28c1df3da8be961cb43225dcf9e30b47d16 Gerrit-Change-Number: 58868 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 20:39:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021