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Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot.
......................................................................
Patch Set 3:
(1 comment)
File src/soc/qualcomm/sc7280/soc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132088):
https://review.coreboot.org/c/coreboot/+/58545/comment/5fe64906_ec0210ea
PS3, Line 27: if (soc_modem_carve_out(&start, &end))
that open brace { should be on the previous line
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Change subject: herobrine: Assert gpio for USB_HUB_LDO_EN
......................................................................
Patch Set 43:
(1 comment)
File src/mainboard/google/herobrine/mainboard.c:
https://review.coreboot.org/c/coreboot/+/55378/comment/a2cba394_215b1805
PS42, Line 23: /* Assert EN_PP3300_HUB for those board variants that use it. */
: if (CONFIG(BOARD_GOOGLE_HEROBRINE)) {
: gpio_output(USB_HUB_LDO_EN, 1);
: } else {
: gpio_output(USB_HUB_LDO_EN, 1);
: }
:
> This condition doesn't seem necessary anymore since the if and else conditions are exactly the same.
Done
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Change subject: sc7280: Add CPUCP firmware support
......................................................................
Patch Set 85:
(1 comment)
File src/soc/qualcomm/sc7280/cpucp_load_reset.c:
https://review.coreboot.org/c/coreboot/+/49768/comment/b501b56e_8094c669
PS82, Line 15: uint32_t val = read32(&epsstop_ptr->access_override);
> Yes, because you're not supposed to write […]
Done
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Change subject: sc7280: Add CPUCP firmware support
......................................................................
Patch Set 85:
(2 comments)
File src/soc/qualcomm/sc7280/include/soc/cpucp.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132078):
https://review.coreboot.org/c/coreboot/+/49768/comment/604c7c24_dc9aa543
PS85, Line 6: #define EPSSTOP_EPSS_TOP (void *)0x18598000
Macros with complex values should be enclosed in parentheses
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132078):
https://review.coreboot.org/c/coreboot/+/49768/comment/af3492be_ed49750e
PS85, Line 7: #define EPSSFAST_BASE_ADDR (void *)0x18580000
Macros with complex values should be enclosed in parentheses
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Hello Shelley Chen, build bot (Jenkins), mturney mturney, Furquan Shaikh, Arthur Heymans, Kyösti Mälkki, Prasad Malisetty,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57614
to look at the new patch set (#18).
Change subject: libpayload: Export PCIe MMCONF from coreboot to libpayload
......................................................................
libpayload: Export PCIe MMCONF from coreboot to libpayload
Add support for passing PCIe MMCONF base from coreboot to
Libpayload. Parsing and saving PCIe MMCONF base address in
lib_sysinfo to allow config access from libpayload arch
specific PCI driver.
Signed-off-by: Prasad Malisetty <pmaliset(a)codeaurora.org>
Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940
---
M payloads/libpayload/Kconfig
M payloads/libpayload/include/coreboot_tables.h
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/coreboot.c
M src/commonlib/include/commonlib/coreboot_tables.h
M src/device/Kconfig
M src/include/boot/coreboot_tables.h
M src/lib/coreboot_table.c
M src/soc/qualcomm/sc7280/Kconfig
9 files changed, 58 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/57614/18
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Hello Shelley Chen, build bot (Jenkins), Julius Werner, Prasad Malisetty, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/53902
to look at the new patch set (#55).
Change subject: sc7280: Add PCIe RC driver in Coreboot
......................................................................
sc7280: Add PCIe RC driver in Coreboot
In coreboot ram stage, PCIe root complex driver initialize
the PCIe core, QMP PHY and does the bus enumeration.
Upon successful detection of EP(NVMe), PCIe RC driver
allocates the resources and set the configuration parameters.
Below are the changes added.
(a) PCIe Core reset, init, link training.
(b) Bus enumeration and resource allocation
(c) QMP PHY 3x2 initialization
To enable NVMe LDO's, need to set gpio19 pin in SKU1
and gpio51 in SKU2.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631
Signed-off-by: Prasad Malisetty <pmaliset(a)codeaurora.org>
---
M src/mainboard/google/herobrine/mainboard.c
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/include/soc/addressmap.h
A src/soc/qualcomm/sc7280/include/soc/pcie.h
A src/soc/qualcomm/sc7280/include/soc/qcom_qmp_phy.h
A src/soc/qualcomm/sc7280/pcie_host.c
6 files changed, 1,693 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/53902/55
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot.
......................................................................
sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot.
modem region to be handled in QC_SEC
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95
---
M src/soc/qualcomm/common/include/soc/symbols_common.h
M src/soc/qualcomm/sc7280/Makefile.inc
A src/soc/qualcomm/sc7280/carve_out.c
M src/soc/qualcomm/sc7280/memlayout.ld
M src/soc/qualcomm/sc7280/soc.c
5 files changed, 35 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/58545/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#20).
Change subject: Herobrine: sc7280: Add support for audio
......................................................................
Herobrine: sc7280: Add support for audio
Add gpio configuration for target specific i2s ports
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org>
Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002
---
M src/mainboard/google/herobrine/board.h
M src/mainboard/google/herobrine/chromeos.c
M src/mainboard/google/herobrine/mainboard.c
3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/57449/20
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Hello build bot (Jenkins), Sandeep Maheswaram,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55378
to look at the new patch set (#43).
Change subject: herobrine: Assert gpio for USB_HUB_LDO_EN
......................................................................
herobrine: Assert gpio for USB_HUB_LDO_EN
Some herobrine variants have USB hub powered by discrete LDO that is
controlled by USB_HUB_LDO_EN gpio. Assert the GPIO on boot.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org>
Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2
---
M src/mainboard/google/herobrine/board.h
M src/mainboard/google/herobrine/mainboard.c
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/55378/43
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