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Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
......................................................................
Set Ready For Review
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Change subject: soc/amd/cezanne: Add ASYNC_FILE_LOADING
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> hmm, i see what the intention behind this one is, but i still find it rather odd
I reworked it to add a new Kconfig.
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Change subject: lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload
......................................................................
lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload
Now that CBFS has this functionality built in, we no longer need to
manually code it.
payload_preload used to use the payload_preload_cache region to store
the raw payload contents. This region was placed outside the firmware
reserved region, so it was available for use by the OS. This was
possible because the payload isn't loaded again on S3 resume.
cbfs_preload only uses the cbfs_cache region. This region must be
reserved because it gets used on the S3 resume path. Unfortunately this
means that cbfs_cache must be increased to hold the payload. Cezanne is
the only platform currently using payload_preload, and the size of
cbfs_cache has already been adjusted.
In the future we could look into adding an option to cbfs_preload that
would allow it to use a different memory pool for the cache allocation.
BUG=b:179699789
TEST=Boot guybrush and verify preloading the payload was successful
CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd
---
M src/include/symbols.h
M src/lib/Kconfig
M src/lib/prog_loaders.c
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/common/block/cpu/Kconfig
M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
6 files changed, 9 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/58962/1
diff --git a/src/include/symbols.h b/src/include/symbols.h
index 52624d4..3e4694b 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -52,7 +52,6 @@
/* Regions for execution units. */
-DECLARE_REGION(payload_preload_cache)
DECLARE_REGION(payload)
/* "program" always refers to the current execution unit. */
DECLARE_REGION(program)
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index 41df1f1..d85d249 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -114,14 +114,3 @@
in the background before they are actually required. This feature
depends on the read-only boot_device having a DMA controller to
perform the background transfer.
-
-config PAYLOAD_PRELOAD
- bool
- depends on COOP_MULTITASKING
- help
- On some systems with SPI DMA controllers, it is possible to preload
- the payload while ramstage is executing. This can be selected by the
- SoC to enable payload preloading.
-
- The SoC needs to define a payload_preload_cache region where the
- raw payload can be placed.
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 1a361ea..8ad646a 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -127,71 +127,37 @@
static struct prog global_payload =
PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload");
-static struct thread_handle payload_preload_handle;
-
-static enum cb_err payload_preload_thread_entry(void *arg)
-{
- size_t size;
- struct prog *payload = &global_payload;
-
- printk(BIOS_DEBUG, "Preloading payload\n");
-
- payload->cbfs_type = CBFS_TYPE_QUERY;
-
- size = cbfs_type_load(prog_name(payload), _payload_preload_cache,
- REGION_SIZE(payload_preload_cache), &payload->cbfs_type);
-
- if (!size) {
- printk(BIOS_ERR, "ERROR: Preloading payload failed\n");
- return CB_ERR;
- }
-
- printk(BIOS_DEBUG, "Preloading payload complete\n");
-
- return CB_SUCCESS;
-}
-
void payload_preload(void)
{
- struct thread_handle *handle = &payload_preload_handle;
-
- if (!CONFIG(PAYLOAD_PRELOAD))
+ if (!CONFIG(CBFS_PRELOAD))
return;
- if (thread_run(handle, payload_preload_thread_entry, NULL))
- printk(BIOS_ERR, "ERROR: Failed to start payload preload thread\n");
+ cbfs_preload(global_payload.name);
}
void payload_load(void)
{
struct prog *payload = &global_payload;
- struct thread_handle *handle = &payload_preload_handle;
- void *mapping = NULL;
- void *buffer;
+ void *mapping;
timestamp_add_now(TS_LOAD_PAYLOAD);
if (prog_locate_hook(payload))
goto out;
- if (CONFIG(PAYLOAD_PRELOAD) && thread_join(handle) == CB_SUCCESS) {
- buffer = _payload_preload_cache;
- } else {
- payload->cbfs_type = CBFS_TYPE_QUERY;
- mapping = cbfs_type_map(prog_name(payload), NULL, &payload->cbfs_type);
- buffer = mapping;
- }
+ payload->cbfs_type = CBFS_TYPE_QUERY;
+ mapping = cbfs_type_map(prog_name(payload), NULL, &payload->cbfs_type);
- if (!buffer)
+ if (!mapping)
goto out;
switch (prog_cbfs_type(payload)) {
case CBFS_TYPE_SELF: /* Simple ELF */
- selfload_mapped(payload, buffer, BM_MEM_RAM);
+ selfload_mapped(payload, mapping, BM_MEM_RAM);
break;
case CBFS_TYPE_FIT: /* Flattened image tree */
if (CONFIG(PAYLOAD_FIT_SUPPORT)) {
- fit_payload(payload, buffer);
+ fit_payload(payload, mapping);
break;
} /* else fall-through */
default:
@@ -200,8 +166,7 @@
break;
}
- if (mapping)
- cbfs_unmap(mapping);
+ cbfs_unmap(mapping);
out:
if (prog_entry(payload) == NULL)
die_with_post_code(POST_INVALID_ROM, "Payload not loaded.\n");
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index dbafa8c..c3e688e 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -196,7 +196,6 @@
select COOP_MULTITASKING
select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
select CBFS_PRELOAD
- select PAYLOAD_PRELOAD
help
When enabled, the platform will use the LPC SPI DMA controller to
asynchronously load contents from the SPI ROM. This will improve
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 3dd1e33..7f50965 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -29,16 +29,6 @@
help
The size of the cbfs_cache region.
-config PAYLOAD_PRELOAD_CACHE_SIZE
- hex
- default 0x30000
- depends on PAYLOAD_PRELOAD
- help
- This config sets the size of the payload_preload_cache memory region.
- It is used as the destination for the raw payload. This space is only
- populated during non-S3, so it doesn't need to be reserved in the
- EARLY_RESERVED_DRAM region.
-
endif # SOC_AMD_COMMON_BLOCK_NONCAR
config SOC_AMD_COMMON_BLOCK_MCA_COMMON
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index a542b7d..e42174f 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -106,16 +106,6 @@
EARLY_RESERVED_DRAM_END(.)
-#if CONFIG(PAYLOAD_PRELOAD)
- /*
- * This section is outside the early_reserved_dram section. We only read
- * the payload on non-S3 boots, so we don't need to reserve it from the
- * OS. The 64 byte alignment is required by the SPI DMA controller.
- */
- . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
- REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, ARCH_CACHELINE_ALIGN_SIZE)
-#endif
-
RAMSTAGE(CONFIG_RAMBASE, 8M)
}
--
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Change subject: soc/amd/cezanne: Enable CBFS_PRELOAD
......................................................................
soc/amd/cezanne: Enable CBFS_PRELOAD
The follow up CLs will use CBFS_PRELOAD. The default CBFS_CACHE_SIZE was
derived by examining the `cbfstool print` output and summing the files
we intend to preload.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/58961/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index a09e9f9..dbafa8c 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -195,6 +195,7 @@
bool "Loads files from SPI asynchronously"
select COOP_MULTITASKING
select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
+ select CBFS_PRELOAD
select PAYLOAD_PRELOAD
help
When enabled, the platform will use the LPC SPI DMA controller to
@@ -202,6 +203,10 @@
boot time because the CPUs can be performing useful work while the
SPI contents are being preloaded.
+config CBFS_CACHE_SIZE
+ hex
+ default 0x40000 if CBFS_PRELOAD
+
config RAMBASE
hex
default 0x10000000
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Add ASYNC_FILE_LOADING
......................................................................
soc/amd/cezanne: Add ASYNC_FILE_LOADING
This gives us a knob that can be controlled via a .config to
enable/disable file preloading. I left the option disabled because
there is currently a race condition that can cause data corruption when
using the SPI DMA controller. The fix will actually introduce a
boot time regression because the preloads are happening at the same time
as the elog init. I want to keep preloading disabled for now until
I get all the sequencing worked out.
BUG=b:179699789
TEST=Boot guybrush and verify no preloading happens.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 11 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/58861/4
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58960 )
Change subject: lib/thread: Start stopwatch after printk
......................................................................
lib/thread: Start stopwatch after printk
We are currently counting how long it takes to print the waiting
message, in addition to the actual time we spent waiting. This results
in inflating the measurement by 1.7ms when the serial console is
enabled. This CL makes it so the print happens before the stopwatch
starts.
BUG=b:179699789
TEST=No longer see printk time taken into account on serial console
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ib48e37c1b2cb462d634141bf767673936aa2dd26
---
M src/lib/thread.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/58960/1
diff --git a/src/lib/thread.c b/src/lib/thread.c
index 7d5cdc5..0393ca7 100644
--- a/src/lib/thread.c
+++ b/src/lib/thread.c
@@ -398,10 +398,10 @@
if (handle->state == THREAD_UNINITIALIZED)
return CB_ERR_ARG;
- stopwatch_init(&sw);
-
printk(BIOS_SPEW, "waiting for thread\n");
+ stopwatch_init(&sw);
+
while (handle->state != THREAD_DONE)
assert(thread_yield() == 0);
--
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Change subject: [WIP] util: Add coreboot Configurator
......................................................................
[WIP] util: Add coreboot Configurator
A simply GUI to change settings in coreboot's CBFS, via the nvramtool utility.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Ie654f6aca57a792be0c295afc081a95ed4d875d1
---
A util/coreboot-configurator/README.md
A util/coreboot-configurator/contrib/PKGBUILD
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A util/coreboot-configurator/contrib/debian/files
A util/coreboot-configurator/contrib/debian/rules
A util/coreboot-configurator/contrib/debian/source/format
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A util/coreboot-configurator/contrib/flatpak/org.coreboot.coreboot-configurator.json
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A util/coreboot-configurator/meson_options.txt
A util/coreboot-configurator/screenshots/coreboot-configurator.gif
A util/coreboot-configurator/screenshots/coreboot-configurator.png
A util/coreboot-configurator/src/application/aboutwindow.cpp
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A util/coreboot-configurator/src/application/aboutwindow.ui
A util/coreboot-configurator/src/application/categories.yaml
A util/coreboot-configurator/src/application/configuration.cpp
A util/coreboot-configurator/src/application/configuration.h
A util/coreboot-configurator/src/application/coreboot_configurator.cpp
A util/coreboot-configurator/src/application/coreboot_configurator.h
A util/coreboot-configurator/src/application/coreboot_configurator.ui
A util/coreboot-configurator/src/application/images.qrc
A util/coreboot-configurator/src/application/main.cpp
A util/coreboot-configurator/src/application/meson.build
A util/coreboot-configurator/src/application/qtyaml.h
A util/coreboot-configurator/src/application/toggle-off.svg
A util/coreboot-configurator/src/application/toggle-on.svg
A util/coreboot-configurator/src/application/toggleswitch.cpp
A util/coreboot-configurator/src/application/toggleswitch.h
A util/coreboot-configurator/src/meson.build
A util/coreboot-configurator/src/static/aboutIcon.png
A util/coreboot-configurator/src/static/coreboot-configurator.desktop
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A util/coreboot-configurator/src/static/org.coreboot.nvramtool.policy
A util/coreboot-configurator/src/static/org.coreboot.reboot.policy
39 files changed, 3,002 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/58854/21
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