coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folder
by Rex-BC Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58935 ) Change subject: soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folder ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Is this patch ok? -- To view, visit https://review.coreboot.org/c/coreboot/+/58935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337 Gerrit-Change-Number: 58935 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Nov 2021 08:44:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Subrata Banik (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Jakub Czapiga, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56628 ) Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... Patch Set 21: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56628/comment/0c8c0303_930a41e0 PS21, Line 20: smbios_form_factor_to_spd_mod_type > suggestion: just use the word `it` here Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 21 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 06:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Subrata Banik (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Jakub Czapiga, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56628 ) Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... Patch Set 21: (1 comment) File src/include/device/dram/spd.h: https://review.coreboot.org/c/coreboot/+/56628/comment/a2b06c52_1bf6a57d PS21, Line 14: __packed > is there a reason this has to be packed? > Reversing the order of the fields would potentially allow better packing by the compiler but I don't know that it matters? Just to avoid compiler optimization and avoid add extra byte for padding. Do you recommend to allow that ? -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 21 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 06:38:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Werner Zeh (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Patrick Rudolph, Felix Held. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 47: (4 comments) File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/55367/comment/116f2844_244cc1c1 PS47, Line 198: config PSE_IMAGE I would rename it to something like "ENABLE_PSE" or the like since with this switch you decide whether to enable or disable the PSE globally. File src/soc/intel/elkhartlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55367/comment/83fc5d03_1fe65859 PS47, Line 58: ifeq ($(CONFIG_PSE_IMAGE),y) : ifeq ($(call int-gt,\ : $(call file-size,$(CONFIG_PSE_IMAGE_FILE))\ : $(shell printf "%d" $(CONFIG_PSE_FW_FILE_SIZE))),\ : 1) You are comparing CONFIG_PSE_FW_FILE_SIZE, which in in KB units, to the real size of the PSE file in byte units. This will never fit. Instead, you need to multiply the CONFIG_PSE_FW_FILE_SIZE by 1024 to get the byte sized buffer. Something the like should work: ifeq ($(call int-gt,\ $(call file-size,$(CONFIG_PSE_IMAGE_FILE))\ $(shell printf "%d" $(call int-shift-left, $(CONFIG_PSE_FW_FILE_SIZE) 10))),\ 1) $(error PSE binary larger than CONFIG_PSE_FW_FILE_SIZE.) endif File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/e9ba74da_66eaa088 PS43, Line 420: params->PchPseShellEnabled = config->PseShellEn; > What's a "PSE shell"? The PSE firmware can (and do in the provided images) have it's own shell on a given, PSE assigned UART. I guess this is more mainboard related and is fine to have the devicetree entry for as it varies from board to board (which UART is used, is it routed, ...?) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/1a2a347f_37b44829 PS47, Line 373: #define psebufsize (CONFIG_PSE_FW_FILE_SIZE + CONFIG_PSE_CONFIG_BUFFER_SIZE) * KiB Move this define somewhere on top of the file? And all defined symbols should be written in upper-case, so PSE_BUF_SIZE would be right and easy to read. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 47 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 06:32:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/haswell/northbridge.c: Drop stale comment
by Werner Zeh (Code Review) 05 Nov '21

05 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58922 ) Change subject: nb/intel/haswell/northbridge.c: Drop stale comment ...................................................................... nb/intel/haswell/northbridge.c: Drop stale comment This can now be controlled with the `MMCONF_BUS_NUMBER` Kconfig option. Change-Id: If0fdefc5b4339acc843443c551892b397ed39c2e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58922 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 2322097..9ead46b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -34,10 +34,6 @@ return NULL; } -/* - * TODO: We could determine how many PCIe buses we need in the bar. - * For now, that number is hardcoded to a max of 64. - */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/58922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0fdefc5b4339acc843443c551892b397ed39c2e Gerrit-Change-Number: 58922 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/kukui: Add new config 'pico6' in coreboot
by Lucas Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: David Wu, Lucas Chen, Shou-Chieh Hsu. Lucas Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58885 ) Change subject: mb/google/kukui: Add new config 'pico6' in coreboot ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9413146913a38ed6a016b6b23ebd6c23040f4469 Gerrit-Change-Number: 58885 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 05:23:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/anahera: Disable autonomous GPIO power management
by Wisley Chen (Code Review) 05 Nov '21

05 Nov '21

Wisley Chen has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/58695 ) Change subject: mb/google/brya/anahera: Disable autonomous GPIO power management ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/58695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9137b6264ee80bc9e00dfdc3ab3926bccb4bf47c Gerrit-Change-Number: 58695 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: revert

1 0

Change in coreboot[master]: Revert "mb/google/brya/anahera: Disable autonomous GPIO power managem...
by Wisley Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Chen Wisley, Tim Wawrzynczak. Hello build bot (Jenkins), Chen Wisley, Tim Wawrzynczak, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58810 to review the following change. Change subject: Revert "mb/google/brya/anahera: Disable autonomous GPIO power management" ...................................................................... Revert "mb/google/brya/anahera: Disable autonomous GPIO power management" This reverts commit 550bdc9050eb97d1c4ddc8d6890cd1713d65ca89. Reason for revert: <It breaks S0ix> Change-Id: I24aa5578aed35319b3613595433329e6aed31fe1 --- M src/mainboard/google/brya/variants/anahera/overridetree.cb 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/58810/1 diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 7d003b3..0225f6c 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -22,17 +22,6 @@ end end chip soc/intel/alderlake - # This disables autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/58810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24aa5578aed35319b3613595433329e6aed31fe1 Gerrit-Change-Number: 58810 Gerrit-PatchSet: 1 Gerrit-Owner: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs
by Kyösti Mälkki (Code Review) 05 Nov '21

05 Nov '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58968 ) Change subject: [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs ...................................................................... [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs It should be optional to protect MRC_CACHE without CHROMEOS so MRC_SETTINGS_PROTECT cannot be enforced from soc/. This change selects MRC_SETTINGS_PROTECT also for older platforms when CHROMEOS is selected. If a board does not implement get_write_protect_state() MRC_SETTINGS_PROTECT should not be selected since the related SPI flash pages will not get protected. Currently, such real implementations may or may not be guarded with CONFIG(CHROMEOS) and the protection is only expected to work after followup works. Change-Id: I8db0394645df1917b686339fa79432ccfc6960a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/mrc_cache/mrc_cache.c M src/ec/lenovo/h8/vboot.c M src/mainboard/amd/majolica/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/galileo/vboot.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/wtm2/chromeos.c M src/security/vboot/bootmode.c M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/vendorcode/google/chromeos/Kconfig 24 files changed, 4 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/58968/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 841c97e..35d5a0c 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -506,6 +506,8 @@ } } +__weak int get_write_protect_state(void) { return 0; } + /* Read flash status register to determine if write protect is active */ static int nvm_is_write_protected(void) { @@ -513,9 +515,6 @@ u8 wp_gpio; u8 wp_spi; - if (!CONFIG(CHROMEOS)) - return 0; - if (!CONFIG(BOOT_DEVICE_SPI_FLASH)) return 0; diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c index b564153..b38151f 100644 --- a/src/ec/lenovo/h8/vboot.c +++ b/src/ec/lenovo/h8/vboot.c @@ -31,12 +31,3 @@ return h8_get_fn_key(); } - -/** - * Only used if CONFIG(CHROMEOS) is set. - * Always zero as the #WP pin of the flash is tied high. - */ -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c index 5fecbe0..3311809 100644 --- a/src/mainboard/amd/majolica/chromeos.c +++ b/src/mainboard/amd/majolica/chromeos.c @@ -1,14 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> -int get_write_protect_state(void) -{ - /* Majolica doesn't have a write protect pin */ - return 0; -} - const struct cros_gpio *variant_cros_gpios(size_t *num) { /* No ChromeOS GPIOs */ diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 4e744f1..79a83f8 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -22,7 +22,3 @@ return 0; } -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index dc2f1b3..4c021cd 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -32,8 +32,3 @@ } #endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index cf90889..1b18664 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -27,8 +27,3 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index 4a7f424..8f627c5 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -17,12 +17,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* Not write protected */ - return 0; -} - void verstage_mainboard_init(void) { const struct reg_script *script; diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index c48a2ce..11e0c7e 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -18,11 +18,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return 0; -} - int __weak get_lid_switch(void) { return -1; diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index b702d23..d76fba4 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -27,8 +27,3 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index b66b4bf..0b9dda6 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -29,8 +29,3 @@ #endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index e026917..6f6c938 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -48,12 +48,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 328429d..39b3597 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -30,8 +30,3 @@ #endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 57d51e79..42566aa 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -25,11 +25,6 @@ return REC_MODE_SETTING; } -int get_write_protect_state(void) -{ - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index c4c6441..ccd0584 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -59,14 +59,8 @@ #if CONFIG(VBOOT_NO_BOARD_SUPPORT) /** - * TODO: Create flash protection interface which implements get_write_protect_state. - * get_recovery_mode_switch should be implemented as default function. + * TODO: get_recovery_mode_switch should be implemented as default function. */ -int __weak get_write_protect_state(void) -{ - return 0; -} - int __weak get_recovery_mode_switch(void) { return 0; diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f646fc7..24df9b8 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -36,7 +36,6 @@ select INTEL_GMA_OPREGION_2_1 select INTEL_TME select MP_SERVICES_PPI_V2 - select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 45e21dd..d6eff1d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -44,7 +44,6 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE - select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_XIP_EARLY_STAGES select NO_PM_ACPI_TIMER diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index f02e810..e9dc961 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -10,7 +10,6 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_HASWELL select INTEL_GMA_ACPI - select MRC_SETTINGS_PROTECT select REG_SCRIPT config BROADWELL_VBOOT_IN_BOOTBLOCK diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 29315a1..0f621c0 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -67,7 +67,6 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PM_ACPI_TIMER_OPTIONAL diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index f23e8d7..501d09d 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -26,7 +26,6 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MP_SERVICES_PPI_V1 - select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 0f0665b..2ff5e3b 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -26,7 +26,6 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MP_SERVICES_PPI_V1 - select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index afa7a23..35df757 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -27,7 +27,6 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MP_SERVICES_PPI_V1 - select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 6c8a376..250eef7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -41,7 +41,6 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PM_ACPI_TIMER_OPTIONAL diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7a78f22..33cae78 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -36,7 +36,6 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MP_SERVICES_PPI_V1 - select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_2 select PM_ACPI_TIMER_OPTIONAL diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 36ca023..6f4d198 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -15,6 +15,7 @@ select CHROMEOS_NVS if ACPI_SOC_NVS select VPD select VBOOT_SLOTS_RW_AB + select MRC_SETTINGS_PROTECT if CACHE_MRC_SETTINGS help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported -- To view, visit https://review.coreboot.org/c/coreboot/+/58968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8db0394645df1917b686339fa79432ccfc6960a2 Gerrit-Change-Number: 58968 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add SPI driver support
by Yu-Ping Wu (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58966 ) Change subject: soc/mediatek/mt8186: Add SPI driver support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Gerrit-Change-Number: 58966 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 03:40:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021