coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/dedede/var/magolor: Enable ELAN touchscreen for magneto
by Tyler Wang (Code Review) 05 Nov '21

05 Nov '21

Tyler Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58967 ) Change subject: mb/google/dedede/var/magolor: Enable ELAN touchscreen for magneto ...................................................................... mb/google/dedede/var/magolor: Enable ELAN touchscreen for magneto Add ELAN touchscreen support for magneto. BUG=b:203122673 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/58967/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa Gerrit-Change-Number: 58967 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/magolor: Enable ELAN touchscreen for magneto
by Tyler Wang (Code Review) 05 Nov '21

05 Nov '21

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58967 ) Change subject: mb/google/dedede/var/magolor: Enable ELAN touchscreen for magneto ...................................................................... mb/google/dedede/var/magolor: Enable ELAN touchscreen for magneto Add ELAN touchscreen support for magneto. BUG=b:203122673 TEST=Build and verify that touchscreen works. Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/58967/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index de82a8a..24b32db 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -19,6 +19,7 @@ option TS_RAYD_0001 4 option TS_WDHT0002 5 option TS_GTCH7503 6 + option TS_ELAN_9004 7 end field AUDIO_CODEC_SOURCE 49 51 option AUDIO_CODEC_UNPROVISIONED 0 @@ -228,6 +229,26 @@ end end chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe TS_SOURCE TS_ELAN_9004 + end + end + chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" -- To view, visit https://review.coreboot.org/c/coreboot/+/58967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa Gerrit-Change-Number: 58967 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/wifi/generic : fix package_size to align with WLAN driver
by Matt Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Sugnan Prabhu S, Matt Chen, Kane Chen. Hello build bot (Jenkins), Sugnan Prabhu S, Kane Chen, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58951 to look at the new patch set (#4). Change subject: drivers/wifi/generic : fix package_size to align with WLAN driver ...................................................................... drivers/wifi/generic : fix package_size to align with WLAN driver Change to use MAX_DSAR_SET_COUNT which WLAN driver always expects 3 no matter what the revision is for EWRD. It will pass the WLAN driver check then to retrieve the data properly. Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Signed-off-by: Matt Chen <matt.chen(a)intel.corp-partner.google.com> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58951/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Gerrit-Change-Number: 58951 Gerrit-PatchSet: 4 Gerrit-Owner: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Janiex Tu <janiex.tu(a)intel.corp-partner.google.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Attention: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add SPI driver support
by Rex-BC Chen (Code Review) 05 Nov '21

05 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58966 ) Change subject: soc/mediatek/mt8186: Add SPI driver support ...................................................................... soc/mediatek/mt8186: Add SPI driver support Add SPI controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Ruwen Liu <ot_ruwen.liu(a)mediatek.com> Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/spi.h M src/soc/mediatek/mt8186/spi.c 3 files changed, 140 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/58966/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index a68d051..cb07ac0 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -6,14 +6,14 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c +bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c wdt.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c -verstage-$(CONFIG_SPI_FLASH) += spi.c +verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c wdt.c @@ -22,7 +22,7 @@ romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-$(CONFIG_SPI_FLASH) += spi.c +romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c wdt.c @@ -30,7 +30,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c +ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h index fbf3995..15e7b91 100644 --- a/src/soc/mediatek/mt8186/include/soc/spi.h +++ b/src/soc/mediatek/mt8186/include/soc/spi.h @@ -8,7 +8,22 @@ #ifndef MTK_MT8186_SPI_H #define MTK_MT8186_SPI_H -#include <spi-generic.h> +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 6 + +#define GET_SCK_REG(x) x->spi_cfg2_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) + +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) + +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) enum { SPI_NOR_GPIO_SET0 = 0, diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c index 4a1c13c..87f669d 100644 --- a/src/soc/mediatek/mt8186/spi.c +++ b/src/soc/mediatek/mt8186/spi.c @@ -7,17 +7,116 @@ #include <assert.h> #include <device/mmio.h> +#include <spi_flash.h> #include <soc/addressmap.h> #include <soc/flash_controller_common.h> #include <soc/gpio.h> #include <soc/spi.h> +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPI0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPI1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(SPI2_CSB), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(SPI3_CSB), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(EINT11), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(SPI5_CSB), + } +}; + struct pad_func { gpio_t gpio; u8 func; }; #define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} +#define PAD_FUNC_GPIO(name) {GPIO(name), 0} + +static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(SPI0_MI, SPI0_MI_A), + PAD_FUNC_GPIO(SPI0_CSB), + PAD_FUNC(SPI0_MO, SPI0_MO_A), + PAD_FUNC(SPI0_CLK, SPI0_CLK_A), + }, + { + PAD_FUNC(SPI1_MI, SPI1_MI_A), + PAD_FUNC_GPIO(SPI1_CSB), + PAD_FUNC(SPI1_MO, SPI1_MO_A), + PAD_FUNC(SPI1_CLK, SPI1_CLK_A), + }, + { + PAD_FUNC(SPI2_MI, SPI2_MI_A), + PAD_FUNC_GPIO(SPI2_CSB), + PAD_FUNC(SPI2_MO, SPI2_MO_A), + PAD_FUNC(SPI2_CK, SPI2_CLK_A), + }, + { + PAD_FUNC(SPI3_MI, SPI3_MI), + PAD_FUNC_GPIO(SPI3_CSB), + PAD_FUNC(SPI3_MO, SPI3_MO), + PAD_FUNC(SPI3_CLK, SPI3_CLK), + }, + { + PAD_FUNC(EINT13, SPI4_MI_A), + PAD_FUNC_GPIO(EINT11), + PAD_FUNC(EINT12, SPI4_MO_A), + PAD_FUNC(EINT10, SPI4_CLK_A), + }, + { + PAD_FUNC(SPI5_MI, SPI5_MI), + PAD_FUNC_GPIO(SPI5_CSB), + PAD_FUNC(SPI5_MO, SPI5_MO), + PAD_FUNC(SPI5_CLK, SPI5_CLK), + }, +}; + +static const struct pad_func pad1_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(EINT3, SPI0_MI_B), + PAD_FUNC_GPIO(EINT1), + PAD_FUNC(EINT2, SPI0_MO_B), + PAD_FUNC(EINT0, SPI0_CLK_B), + }, + { + PAD_FUNC(EINT9, SPI1_MI_B), + PAD_FUNC_GPIO(EINT7), + PAD_FUNC(EINT8, SPI1_MO_B), + PAD_FUNC(EINT6, SPI1_CLK_B), + }, + { + PAD_FUNC(CAM_PDN1, SPI2_MI_B), + PAD_FUNC_GPIO(CAM_PDN0), + PAD_FUNC(CAM_RST0, SPI2_MO_B), + PAD_FUNC(EINT18, SPI2_CLK_B), + }, + { + }, + { + PAD_FUNC(I2S2_DI, SPI4_MI_B), + PAD_FUNC_GPIO(I2S2_BCK), + PAD_FUNC(I2S2_LRCK, SPI4_MO_B), + PAD_FUNC(I2S2_MCK, SPI4_CLK_B), + }, + { + }, +}; static const struct pad_func nor_pinmux[SPI_NOR_GPIO_SET_NUM][4] = { /* GPIO 36 ~ 39 */ @@ -49,6 +148,22 @@ } } +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + const struct pad_func *ptr; + + if (pad_select == SPI_PAD0_MASK) { + ptr = pad0_funcs[bus]; + } else { + assert((bus == 0 || bus == 1 || bus == 2 || bus == 4) && + pad_select == SPI_PAD1_MASK); + ptr = pad1_funcs[bus]; + } + for (int i = 0; i < 4; i++) + gpio_set_mode(ptr[i].gpio, ptr[i].func); +} + static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, @@ -56,6 +171,11 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, + { .ctrlr = &spi_flash_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, -- To view, visit https://review.coreboot.org/c/coreboot/+/58966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Gerrit-Change-Number: 58966 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] util: Add coreboot Configurator
by Martin Roth (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Sean Rhodes, Matt DeVillier, Tim Wawrzynczak, Angel Pons. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58854 ) Change subject: [WIP] util: Add coreboot Configurator ...................................................................... Patch Set 25: (1 comment) File util/coreboot-configurator/src/application/coreboot_configurator.cpp: https://review.coreboot.org/c/coreboot/+/58854/comment/1ec3db29_2ffe01e7 PS25, Line 206: This is the reason for the jenkins build failure. You can see that by drilling down into the failure log: https://qa.coreboot.org/job/coreboot-gerrit/186288/testReport/(root)/lint/l… -- To view, visit https://review.coreboot.org/c/coreboot/+/58854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie654f6aca57a792be0c295afc081a95ed4d875d1 Gerrit-Change-Number: 58854 Gerrit-PatchSet: 25 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 02:11:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS A/B recovery feature
by Bao Zheng (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56773 ) Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature ...................................................................... Patch Set 29: (4 comments) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/56773/comment/79ab8f06_e80e28a4 PS29, Line 769: pspdir2 pspdir2 != NULL https://review.coreboot.org/c/coreboot/+/56773/comment/abae94f4_6a36e8a3 PS29, Line 775: pspdir2 same. https://review.coreboot.org/c/coreboot/+/56773/comment/ad94ea15_7eee0405 PS29, Line 792: uint8_t fw_type type https://review.coreboot.org/c/coreboot/+/56773/comment/c8b7e044_17902159 PS29, Line 796: type (uint8_t)type -- To view, visit https://review.coreboot.org/c/coreboot/+/56773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Gerrit-Change-Number: 56773 Gerrit-PatchSet: 29 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 01:49:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
by Tim Wawrzynczak (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Felix Singer, Sean Rhodes, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58798 ) Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS ...................................................................... Patch Set 9: (1 comment) Patchset: PS5: > Yup - using S3 so disabling it is par for the course. […] This is probably `_PR3` right? Including the `_PR3` method indicates support for D3cold in the latest ACPI spec. Maybe try removing _PR3? That should indicate that it should turn off in D3hot (what device state does Linux put it in for S3?) -- To view, visit https://review.coreboot.org/c/coreboot/+/58798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Gerrit-Change-Number: 58798 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 05 Nov 2021 01:31:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/elog/elog: Add timestamps to elog_init
by Tim Wawrzynczak (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Raul Rangel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58957 ) Change subject: drivers/elog/elog: Add timestamps to elog_init ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f Gerrit-Change-Number: 58957 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Nov 2021 01:25:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Adjust I2C speed
by shkim (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: SH Kim. Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58965 to review the following change. Change subject: mb/google/dedede/var/bugzzy: Adjust I2C speed ...................................................................... mb/google/dedede/var/bugzzy: Adjust I2C speed This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns and fall_time_ns values for each port are capured by a scope. BUG=None BRANCH=dedede TEST=built and verified adjusted I2C speed < 400KHz Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023 --- M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/58965/1 diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index 453d8c3..fd509cb 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -63,12 +63,18 @@ }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 133, + .fall_time_ns = 29, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 227, + .fall_time_ns = 9, }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 91, + .fall_time_ns = 2, }, .i2c[4] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/58965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023 Gerrit-Change-Number: 58965 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Update charger performance control table
by SH Kim (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: shkim, Paul Menzel, Karthik Ramasubramanian. SH Kim has uploaded a new patch set (#3) to the change originally created by shkim. ( https://review.coreboot.org/c/coreboot/+/58840 ) Change subject: mb/google/dedede/var/bugzzy: Update charger performance control table ...................................................................... mb/google/dedede/var/bugzzy: Update charger performance control table Update charger performance control table of DPTF for bugzzy. Since the EC change chromium:197776876 modified maximum charging current to reduce skin temperature, this change adjusts the charging performance table with the modified value. BUG=b:197776876 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9 --- M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58840/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9 Gerrit-Change-Number: 58840 Gerrit-PatchSet: 3 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: shkim <sh_.kim(a)samsung.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021