coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
by Shou-Chieh Hsu (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Henry Sun, Frank Chu, Karthik Ramasubramanian. Shou-Chieh Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58734 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Gerrit-Change-Number: 58734 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 10:11:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by flora.fu＠mediatek.com (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58969 to look at the new patch set (#2). Change subject: soc/mediatek/mt8195: Add APU device apc driver ...................................................................... soc/mediatek/mt8195: Add APU device apc driver Add APU device apc driver and setup permissions. BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu(a)mediatek.com> Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h 6 files changed, 524 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58969/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Gerrit-Change-Number: 58969 Gerrit-PatchSet: 2 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/wifi/generic : fix package_size to align with WLAN driver
by Matt Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Sugnan Prabhu S, Paul Menzel, Kane Chen. Hello build bot (Jenkins), Sugnan Prabhu S, Kane Chen, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58951 to look at the new patch set (#5). Change subject: drivers/wifi/generic : fix package_size to align with WLAN driver ...................................................................... drivers/wifi/generic : fix package_size to align with WLAN driver Change to use MAX_DSAR_SET_COUNT which WLAN driver always expects 3 no matter what the revision is for EWRD. It will pass the WLAN driver check then to retrieve the data properly. BUG=b:204414616 TEST= tested on brya with DRTU tool to verify if SAR table is read properly or not. Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Signed-off-by: Matt Chen <matt.chen(a)intel.corp-partner.google.com> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58951/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Gerrit-Change-Number: 58951 Gerrit-PatchSet: 5 Gerrit-Owner: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Janiex Tu <janiex.tu(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by flora.fu＠mediatek.com (Code Review) 05 Nov '21

05 Nov '21

flora.fu(a)mediatek.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58969 ) Change subject: soc/mediatek/mt8195: Add APU device apc driver ...................................................................... soc/mediatek/mt8195: Add APU device apc driver Add APU device apc driver and setup permissions. BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu(a)mediatek.com> Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h 6 files changed, 523 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58969/1 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index f99fa33..8cec51d 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -23,6 +23,7 @@ verstage-y += ../common/wdt.c ramstage-y += apusys.c +ramstage-y += apusys_devapc.c romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += ../common/clkbuf.c diff --git a/src/soc/mediatek/mt8195/apusys_devapc.c b/src/soc/mediatek/mt8195/apusys_devapc.c new file mode 100644 index 0000000..3a7b9d0 --- /dev/null +++ b/src/soc/mediatek/mt8195/apusys_devapc.c @@ -0,0 +1,408 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/apusys_devapc.h> +#include <soc/apusys_devapc_def.h> + +/* For AO-0, AO-1 */ +#define SLAVE_FORBID_EXCEPT_D0_NO_PORTECT(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN) + +/* For AO-5 */ +#define SLAVE_NO_PROTECT_EXCEPT_D0_SEC_RW(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + SEC_RW_ONLY, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION) + +/* For VPUs */ +#define SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN) + +/* For Reviser, AO, DPAC, IOMMU Bank1~4 */ +#define SLAVE_FORBID_EXCEPT_D0_SEC_RW(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN) + +/* For apu_noc_config_0/1/2 */ +#define SLAVE_FORBID_EXCEPT_D0_D3_NO_PORTECT(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN) + +/* For Others */ +#define SLAVE_NO_PROTECT(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION) + + +/* NOC DAPC */ +static const struct APC_DOM_16 APUSYS_NOC_DAPC_AO[] = { +/* 0 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv00-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv00-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv00-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv01-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv01-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv01-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-3"), +/* 10 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv04_05_06_07-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv04_05_06_07-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv04_05_06_07-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv04_05_06_07-3"), +}; + +static const struct APC_DOM_16 APUSYS_AO_Devices[] = { +/* 0 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-1"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apusys_ao-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-3"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-5"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-6"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apusys_ao-8"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apusys_ao-9"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("md32_apb_s-0"), + +/* 10 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("md32_apb_s-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("md32_apb_s-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("md32_debug_apb"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_con2_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_con1_config"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_sctrl_reviscer"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_sema_stimer"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_emi_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_edma0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_edma1"), + +/* 20 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_cpe_sensor"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_cpe_coef"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_cpe_ctrl"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_sensor_wrp_dla_0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_sensor_wrp_dla_1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_dapc_ao"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_dapc"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("infra_bcrm"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("infra_ao_bcrm"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("noc_dapc"), + +/* 30 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_noc_bcrm"), +SLAVE_FORBID_EXCEPT_D0_D3_NO_PORTECT("apu_noc_config_0"), +SLAVE_FORBID_EXCEPT_D0_D3_NO_PORTECT("apu_noc_config_1"), +SLAVE_FORBID_EXCEPT_D0_D3_NO_PORTECT("apu_noc_config_2"), +SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT("vpu_core0_config-0"), +SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT("vpu_core0_config-1"), +SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT("vpu_core1_config-0"), +SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT("vpu_core1_config-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla0_apb-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla0_apb-1"), + +/* 40 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla0_apb-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla0_apb-3"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla1_apb-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla1_apb-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla1_apb-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla1_apb-3"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_iommu0_r0"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu0_r1"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu0_r2"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu0_r3"), + +/* 50 */ +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu0_r4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_iommu1_r0"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu1_r1"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu1_r2"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu1_r3"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu1_r4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_rsi2_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_s0_ssc_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_n0_ssc_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_acp_ssc_config"), + +/* 60 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_s1_ssc_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_n1_ssc_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-3"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-5"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("vpu_core0_debug_apb"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("vpu_core1_debug_apb"), + +/* 70 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apb_infra_dbg_ctl"), +}; + +static int set_slave_noc_dapc(u32 slave, + enum APUSYS_APC_DOMAIN_ID domain_id, + enum APUSYS_APC_PERM_TYPE perm) +{ + u32 apc_register_index; + u32 apc_set_index; + u32 *base = NULL; + u32 clr_bit; + u32 set_bit; + int ret; + + if (perm >= PERM_NUM || perm < 0) { + printk(BIOS_DEBUG, "[NOC_DAPC] permission type:0x%x is not supported!\n", + perm); + ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + goto exit; + } + + apc_register_index = slave / APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + + clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2)); + set_bit = ((u32)perm) << (apc_set_index * 2); + + if (slave < APUSYS_NOC_DAPC_AO_SLAVE_NUM && + domain_id < APUSYS_NOC_DAPC_AO_DOM_NUM) { + base = (u32 *)((size_t)APUSYS_NOC_DAPC_AO_BASE + + domain_id * 0x40 + apc_register_index * 4); + apuapc_writel(apuapc_readl(base) & clr_bit, base); + apuapc_writel(apuapc_readl(base) | set_bit, base); + ret = APUSYS_APC_OK; + } else { + printk(BIOS_DEBUG, "[NOC_DAPC] %s: %s, %s:0x%x, %s:0x%x\n", + __func__, "out of boundary", + "slave", slave, + "domain_id", domain_id); + ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + +exit: + return ret; +} + +static void dump_apusys_noc_dapc(void) +{ + u32 reg_num; + u32 d, i; + + reg_num = APUSYS_NOC_DAPC_AO_SLAVE_NUM / + APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) { + for (i = 0U; i <= reg_num; i++) + printk(BIOS_DEBUG, "[NOCDAPC] D%d_APC_%d: 0x%x\n", d, i, + apuapc_readl(APUSYS_NOC_DAPC_AO_BASE + + d * 0x40 + i * 4)); + } + printk(BIOS_DEBUG, "[NOCDAPC] APC_CON: 0x%x\n", + apuapc_readl(APUSYS_NOC_DAPC_CON)); +} + +static int set_slave_apc(u32 slave, + enum APUSYS_APC_DOMAIN_ID domain_id, + enum APUSYS_APC_PERM_TYPE perm) +{ + u32 apc_register_index; + u32 apc_set_index; + u32 *base = NULL; + u32 clr_bit; + u32 set_bit; + int ret; + + if (perm >= PERM_NUM) { + printk(BIOS_DEBUG, "[APUAPC] perm type:0x%x is not supported!\n", + perm); + ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + goto exit; + } + + apc_register_index = slave / APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + + clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2)); + set_bit = perm << (apc_set_index * 2); + + if (slave < APUSYS_APC_SYS0_AO_SLAVE_NUM && + domain_id < APUSYS_APC_SYS0_AO_DOM_NUM) { + base = (u32 *)((size_t)APUSYS_APC_AO_BASE + + domain_id * 0x40 + apc_register_index * 4); + apuapc_writel(apuapc_readl(base) & clr_bit, base); + apuapc_writel(apuapc_readl(base) | set_bit, base); + ret = APUSYS_APC_OK; + } else { + printk(BIOS_DEBUG, "[APUAPC] %s: %s, %s:0x%x, %s:0x%x\n", + __func__, "out of boundary", + "slave", slave, + "domain_id", domain_id); + ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + +exit: + return ret; +} + +static void dump_apusys_ao_apc(void) +{ + u32 reg_num; + u32 d, i; + + reg_num = APUSYS_APC_SYS0_AO_SLAVE_NUM / + APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) { + for (i = 0U; i <= reg_num; i++) + printk(BIOS_DEBUG, "[APUAPC] D%d_APC_%d: 0x%x\n", d, i, + apuapc_readl(APUSYS_APC_AO_BASE + + d * 0x40 + i * 4)); + } + printk(BIOS_DEBUG, "[APUAPC] APC_CON: 0x%x\n", + apuapc_readl(APUSYS_APC_CON)); +} + +static int set_apusys_noc_dapc(void) +{ + int ret = APUSYS_APC_OK; + u32 i; + + for (i = 0; i < ARRAY_SIZE(APUSYS_NOC_DAPC_AO); i++) { + ret += set_slave_noc_dapc(i, DOMAIN_0, + APUSYS_NOC_DAPC_AO[i].d0_permission); + ret += set_slave_noc_dapc(i, DOMAIN_1, + APUSYS_NOC_DAPC_AO[i].d1_permission); + ret += set_slave_noc_dapc(i, DOMAIN_2, + APUSYS_NOC_DAPC_AO[i].d2_permission); + ret += set_slave_noc_dapc(i, DOMAIN_3, + APUSYS_NOC_DAPC_AO[i].d3_permission); + ret += set_slave_noc_dapc(i, DOMAIN_4, + APUSYS_NOC_DAPC_AO[i].d4_permission); + ret += set_slave_noc_dapc(i, DOMAIN_5, + APUSYS_NOC_DAPC_AO[i].d5_permission); + ret += set_slave_noc_dapc(i, DOMAIN_6, + APUSYS_NOC_DAPC_AO[i].d6_permission); + ret += set_slave_noc_dapc(i, DOMAIN_7, + APUSYS_NOC_DAPC_AO[i].d7_permission); + ret += set_slave_noc_dapc(i, DOMAIN_8, + APUSYS_NOC_DAPC_AO[i].d8_permission); + ret += set_slave_noc_dapc(i, DOMAIN_9, + APUSYS_NOC_DAPC_AO[i].d9_permission); + ret += set_slave_noc_dapc(i, DOMAIN_10, + APUSYS_NOC_DAPC_AO[i].d10_permission); + ret += set_slave_noc_dapc(i, DOMAIN_11, + APUSYS_NOC_DAPC_AO[i].d11_permission); + ret += set_slave_noc_dapc(i, DOMAIN_12, + APUSYS_NOC_DAPC_AO[i].d12_permission); + ret += set_slave_noc_dapc(i, DOMAIN_13, + APUSYS_NOC_DAPC_AO[i].d13_permission); + ret += set_slave_noc_dapc(i, DOMAIN_14, + APUSYS_NOC_DAPC_AO[i].d14_permission); + ret += set_slave_noc_dapc(i, DOMAIN_15, + APUSYS_NOC_DAPC_AO[i].d15_permission); + } + + return ret; +} + +static int32_t set_apusys_ao_apc(void) +{ + int ret = APUSYS_APC_OK; + u32 i; + + for (i = 0; i < ARRAY_SIZE(APUSYS_AO_Devices); i++) { + /* d0: APMCU */ + ret += set_slave_apc(i, DOMAIN_0, + APUSYS_AO_Devices[i].d0_permission); + ret += set_slave_apc(i, DOMAIN_1, + APUSYS_AO_Devices[i].d1_permission); + ret += set_slave_apc(i, DOMAIN_2, + APUSYS_AO_Devices[i].d2_permission); + ret += set_slave_apc(i, DOMAIN_3, + APUSYS_AO_Devices[i].d3_permission); + ret += set_slave_apc(i, DOMAIN_4, + APUSYS_AO_Devices[i].d4_permission); + ret += set_slave_apc(i, DOMAIN_5, + APUSYS_AO_Devices[i].d5_permission); + ret += set_slave_apc(i, DOMAIN_6, + APUSYS_AO_Devices[i].d6_permission); + ret += set_slave_apc(i, DOMAIN_7, + APUSYS_AO_Devices[i].d7_permission); + ret += set_slave_apc(i, DOMAIN_8, + APUSYS_AO_Devices[i].d8_permission); + ret += set_slave_apc(i, DOMAIN_9, + APUSYS_AO_Devices[i].d9_permission); + ret += set_slave_apc(i, DOMAIN_10, + APUSYS_AO_Devices[i].d10_permission); + ret += set_slave_apc(i, DOMAIN_11, + APUSYS_AO_Devices[i].d11_permission); + ret += set_slave_apc(i, DOMAIN_12, + APUSYS_AO_Devices[i].d12_permission); + ret += set_slave_apc(i, DOMAIN_13, + APUSYS_AO_Devices[i].d13_permission); + ret += set_slave_apc(i, DOMAIN_14, + APUSYS_AO_Devices[i].d14_permission); + ret += set_slave_apc(i, DOMAIN_15, + APUSYS_AO_Devices[i].d15_permission); + } + + return ret; +} + +static void set_apc_lock(void) +{ + /* Lock apu_sctrl_reviser */ + u32 set_bit = 1U << APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER; + + set_bit = set_bit | (1U << APUSYS_APC_SYS0_LOCK_BIT_DEVAPC_AO_WRAPPER); + apuapc_writel(set_bit, APUSYS_SYS0_APC_LOCK_0); +} + +void start_apusys_devapc(void) +{ + int ret = APUSYS_APC_OK; + + /* Check violation status */ + printk(BIOS_DEBUG, "[APUAPC] vio %d\n", + apuapc_readl(APUSYS_APC_CON) & 0x80000000); + + /* Initial Permission */ + ret = set_apusys_ao_apc(); + printk(BIOS_DEBUG, "[APUAPC] %s - %s!\n", "set_apusys_ao_apc", + ret ? "FAILED" : "SUCCESS"); + + /* Lock */ + set_apc_lock(); + + /* Initial NoC Permission */ + ret = set_apusys_noc_dapc(); + printk(BIOS_DEBUG, "[APUAPC] %s - %s!\n", "set_apusys_noc_dapc", + ret ? "FAILED" : "SUCCESS"); + + dump_apusys_ao_apc(); + dump_apusys_noc_dapc(); + + printk(BIOS_DEBUG, "[APUAPC] %s done\n", __func__); +} + diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index 9354353..3639ad5 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <soc/devapc.h> +#include <soc/apusys_devapc.h> static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { /* 0 */ @@ -1884,4 +1885,7 @@ if (devapc_init[i].dump) devapc_init[i].dump(devapc_ao_base); } + + /* Setup APUSYS Permission */ + start_apusys_devapc(); } diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index cbe704c..d9486b3 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -81,6 +81,8 @@ IOCFG_TL_BASE = IO_PHYS + 0x01F40000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, APU_MBOX_BASE = IO_PHYS + 0x09000000, + APUSYS_APC_AO_BASE = IO_PHYS + 0x090F8000, + APUSYS_NOC_DAPC_AO_BASE = IO_PHYS + 0x090FC000, DISP_OVL0_BASE = IO_PHYS + 0x0C000000, DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, diff --git a/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h b/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h new file mode 100644 index 0000000..fa8cb80 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef APUSYS_DEVAPC_H +#define APUSYS_DEVAPC_H + +void start_apusys_devapc(void); + +#endif /* APUSYS_DEVAPC_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h b/src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h new file mode 100644 index 0000000..e0d7cbf --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef APUSYS_DEVAPC_DEF_H +#define APUSYS_DEVAPC_DEF_H + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <types.h> + +enum APUSYS_APC_ERR_STATUS { + APUSYS_APC_OK = 0x0, + + APUSYS_APC_ERR_GENERIC = 0x1000, + APUSYS_APC_ERR_INVALID_CMD = 0x1001, + APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002, + APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003, + APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004, + APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005, + APUSYS_APC_ERR_OUT_OF_BOUNDARY = 0x1006, + APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED = 0x1007, +}; + +enum APUSYS_APC_PERM_TYPE { + NO_PROTECTION = 0U, + SEC_RW_ONLY = 1U, + SEC_RW_NS_R = 2U, + FORBIDDEN = 3U, + PERM_NUM = 4U, +}; + +enum APUSYS_APC_DOMAIN_ID { + DOMAIN_0 = 0U, + DOMAIN_1 = 1U, + DOMAIN_2 = 2U, + DOMAIN_3 = 3U, + DOMAIN_4 = 4U, + DOMAIN_5 = 5U, + DOMAIN_6 = 6U, + DOMAIN_7 = 7U, + DOMAIN_8 = 8U, + DOMAIN_9 = 9U, + DOMAIN_10 = 10U, + DOMAIN_11 = 11U, + DOMAIN_12 = 12U, + DOMAIN_13 = 13U, + DOMAIN_14 = 14U, + DOMAIN_15 = 15U, +}; + +struct APC_DOM_16 { + unsigned char d0_permission; + unsigned char d1_permission; + unsigned char d2_permission; + unsigned char d3_permission; + unsigned char d4_permission; + unsigned char d5_permission; + unsigned char d6_permission; + unsigned char d7_permission; + unsigned char d8_permission; + unsigned char d9_permission; + unsigned char d10_permission; + unsigned char d11_permission; + unsigned char d12_permission; + unsigned char d13_permission; + unsigned char d14_permission; + unsigned char d15_permission; +}; + +#define APUSYS_APC_AO_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) \ + {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \ + (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \ + (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \ + (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \ + (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \ + (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \ + (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15} + +#define apuapc_writel(val, reg) write32((void *)reg, val) +#define apuapc_readl(reg) read32((void *)reg) + +#define APUSYS_APC_CON ((u32 *)(APUSYS_APC_AO_BASE + 0x00F00)) +#define APUSYS_SYS0_APC_LOCK_0 ((u32 *)(APUSYS_APC_AO_BASE + 0x00700)) +#define APUSYS_NOC_DAPC_CON ((u32 *)(APUSYS_NOC_DAPC_AO_BASE + 0x00F00)) + +#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_APC_SYS0_AO_DOM_NUM 16U +#define APUSYS_APC_SYS0_AO_SLAVE_NUM 71U + +#define APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER 15U +#define APUSYS_APC_SYS0_LOCK_BIT_DEVAPC_AO_WRAPPER 8U + +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_NOC_DAPC_AO_DOM_NUM 16U +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM 27U +#endif /* APUSYS_DEVAPC_DEF_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Gerrit-Change-Number: 58969 Gerrit-PatchSet: 1 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Michael Niewöhner (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 47: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/b912f4f3_b8fe1f9a PS43, Line 420: params->PchPseShellEnabled = config->PseShellEn; > The PSE firmware can (and do in the provided images) have it's own shell on a given, PSE assigned UA […] Well, this is about enabling/disabling it. If it just doesn't matter that it's always enabled, we probably can keep it that way. However, it *might* make sense to treat it like coreboot console. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 47 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 09:37:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/wifi/generic : fix package_size to align with WLAN driver
by Matt Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Sugnan Prabhu S, Paul Menzel, Kane Chen. Matt Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58951 ) Change subject: drivers/wifi/generic : fix package_size to align with WLAN driver ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58951/comment/015ef240_351bd944 PS4, Line 7: drivers/wifi/generic : > Please remove the space before the colon. OK, will do. https://review.coreboot.org/c/coreboot/+/58951/comment/2b4bee15_ae871d2c PS4, Line 11: the WLAN driver check > What WLAN driver is that exactly? This Intel WiFi driver, where is in kernel drivers/net/wireless/intel/iwlwifi/fw/acpi.c. The variable sar->dsar_set_count is always 1 in CB, where WLAN driver expects 3[1]. [1] #define ACPI_SAR_PROFILE_NUM 4 #define ACPI_EWRD_WIFI_DATA_SIZE_REV2 ((ACPI_SAR_PROFILE_NUM - 1) * \ ACPI_SAR_NUM_CHAINS_REV2 * \ ACPI_SAR_NUM_SUB_BANDS_REV2 + 3) Then (ACPI_SAR_PROFILE_NUM - 1) is 3. -- To view, visit https://review.coreboot.org/c/coreboot/+/58951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Gerrit-Change-Number: 58951 Gerrit-PatchSet: 4 Gerrit-Owner: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Janiex Tu <janiex.tu(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 09:34:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8186 Corsola review ToT
by Rex-BC Chen (Code Review) 05 Nov '21

05 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58639 to look at the new patch set (#17). Change subject: DO-NOT-SUBMIT: MT8186 Corsola review ToT ...................................................................... DO-NOT-SUBMIT: MT8186 Corsola review ToT Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 --- M README.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58639/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/58639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f304822c426417bb58037daa536bfb8dda1db3 Gerrit-Change-Number: 58639 Gerrit-PatchSet: 17 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add SPI driver support
by Rex-BC Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58966 to look at the new patch set (#3). Change subject: soc/mediatek/mt8186: Add SPI driver support ...................................................................... soc/mediatek/mt8186: Add SPI driver support Add SPI controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Ruwen Liu <ot_ruwen.liu(a)mediatek.com> Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/spi.h M src/soc/mediatek/mt8186/spi.c 3 files changed, 140 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/58966/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Gerrit-Change-Number: 58966 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Enable and initialize EINT
by Rex-BC Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58938 to look at the new patch set (#6). Change subject: soc/mediatek/mt8186: Enable and initialize EINT ...................................................................... soc/mediatek/mt8186: Enable and initialize EINT EINT event mask register is used to mask EINT wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel EINT upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I84946c2c74dd233419cb94f013a42c734363baf7 --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/bootblock.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/58938/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84946c2c74dd233419cb94f013a42c734363baf7 Gerrit-Change-Number: 58938 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Add timer support
by Rex-BC Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58937 to look at the new patch set (#6). Change subject: soc/mediatek/mt8186: Add timer support ...................................................................... soc/mediatek/mt8186: Add timer support Add timer drivers to use timer function. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I6524e4dec4cbe7f7eb75a7940c329416559a03c8 --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/timer.c 2 files changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/58937/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6524e4dec4cbe7f7eb75a7940c329416559a03c8 Gerrit-Change-Number: 58937 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021