coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()`
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58913 ) Change subject: soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()` ...................................................................... soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()` Rewrite level type check and use unsigned types. In addition, also use unsigned types in the `get_cpu_count()` function. Change-Id: I63f236f0f94f9412ec03ae25781befe619cf7c1f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58913 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 10 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 44cb297..126a1c6 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -162,21 +162,20 @@ *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } -static int detect_num_cpus_via_cpuid(void) +static unsigned int detect_num_cpus_via_cpuid(void) { - register int ecx = 0; - struct cpuid_result leaf_b; + unsigned int ecx = 0; while (1) { - leaf_b = cpuid_ext(0xb, ecx); + const struct cpuid_result leaf_b = cpuid_ext(0xb, ecx); /* Processor doesn't have hyperthreading so just determine the - * number of cores by from level type (ecx[15:8] == * 2). */ - if ((leaf_b.ecx & 0xff00) == 0x0200) - break; + number of cores from level type (ecx[15:8] == 2). */ + if ((leaf_b.ecx >> 8 & 0xff) == 2) + return leaf_b.ebx & 0xffff; + ecx++; } - return (leaf_b.ebx & 0xffff); } static int detect_num_cpus_via_mch(void) @@ -209,11 +208,11 @@ /* Find CPU topology */ int get_cpu_count(void) { - int num_cpus = detect_num_cpus_via_mch(); + unsigned int num_cpus = detect_num_cpus_via_mch(); - if (num_cpus <= 0 || num_cpus > CONFIG_MAX_CPUS) { + if (num_cpus == 0 || num_cpus > CONFIG_MAX_CPUS) { num_cpus = detect_num_cpus_via_cpuid(); - printk(BIOS_DEBUG, "Number of Cores (CPUID): %d.\n", num_cpus); + printk(BIOS_DEBUG, "Number of Cores (CPUID): %u.\n", num_cpus); } return num_cpus; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f236f0f94f9412ec03ae25781befe619cf7c1f Gerrit-Change-Number: 58913 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp: Refactor `get_threads_per_package()`
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58914 ) Change subject: soc/intel/xeon_sp: Refactor `get_threads_per_package()` ...................................................................... soc/intel/xeon_sp: Refactor `get_threads_per_package()` Reduce the visibility of the `get_threads_per_package()` function and retype its return value to `unsigned int`. Change-Id: Ie71730d9a89eb7c4bb82d09d140fbcec7a6fe5f3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58914 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/util.c 2 files changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 26bb3c3..213735a 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -9,7 +9,6 @@ void unlock_pam_regions(void); uint8_t get_stack_busno(const uint8_t stack); msr_t read_msr_ppin(void); -int get_threads_per_package(void); int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 579ebbc..4295704 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -74,7 +74,7 @@ return ppin; } -int get_threads_per_package(void) +static unsigned int get_threads_per_package(void) { unsigned int core_count, thread_count; cpu_read_topology(&core_count, &thread_count); -- To view, visit https://review.coreboot.org/c/coreboot/+/58914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71730d9a89eb7c4bb82d09d140fbcec7a6fe5f3 Gerrit-Change-Number: 58914 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/braswell: Make `num_cpus` unsigned
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58915 ) Change subject: soc/intel/braswell: Make `num_cpus` unsigned ...................................................................... soc/intel/braswell: Make `num_cpus` unsigned Change-Id: Iff6da3dc9c744a3dae3f4dd4ac37a91f348450a3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58915 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/intel/braswell/include/soc/pattrs.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h index 5cad6d0..3383589 100644 --- a/src/soc/intel/braswell/include/soc/pattrs.h +++ b/src/soc/intel/braswell/include/soc/pattrs.h @@ -29,7 +29,7 @@ int stepping; const void *microcode_patch; int address_bits; - int num_cpus; + unsigned int num_cpus; unsigned int bclk_khz; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/58915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff6da3dc9c744a3dae3f4dd4ac37a91f348450a3 Gerrit-Change-Number: 58915 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/baytrail: Make `num_cpus` unsigned
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58916 ) Change subject: soc/intel/baytrail: Make `num_cpus` unsigned ...................................................................... soc/intel/baytrail: Make `num_cpus` unsigned Change-Id: I9ab0106c27a834d5d2ac1cb8023f4400a8ad91cd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58916 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/intel/baytrail/include/soc/pattrs.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h index cd22e12..d0d3bf0 100644 --- a/src/soc/intel/baytrail/include/soc/pattrs.h +++ b/src/soc/intel/baytrail/include/soc/pattrs.h @@ -29,7 +29,7 @@ int stepping; const void *microcode_patch; int address_bits; - int num_cpus; + unsigned int num_cpus; unsigned int bclk_khz; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/58916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ab0106c27a834d5d2ac1cb8023f4400a8ad91cd Gerrit-Change-Number: 58916 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: google/guybrush: Move SPI speed override
by Kyösti Mälkki (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Karthik Ramasubramanian, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58945 ) Change subject: google/guybrush: Move SPI speed override ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > yes, i'd say that the filename describes well what it does Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Gerrit-Change-Number: 58945 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 11:36:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: google/guybrush: Move SPI speed override
by Kyösti Mälkki (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Kyösti Mälkki, Karthik Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58945 to look at the new patch set (#2). Change subject: google/guybrush: Move SPI speed override ...................................................................... google/guybrush: Move SPI speed override SPI speed override is not related to ChromeOS, thus the location in chromeos.c was poor choice. Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/guybrush/Makefile.inc M src/mainboard/google/guybrush/chromeos.c A src/mainboard/google/guybrush/spi_speeds.c 3 files changed, 15 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/58945/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Gerrit-Change-Number: 58945 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
by Marco Chen (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Henry Sun, Frank Chu, Zhuohao Lee, Karthik Ramasubramanian. Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58734 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/dedede/variants/galtic/variant.c: https://review.coreboot.org/c/coreboot/+/58734/comment/c74f4ba8_16ae4f8a PS5, Line 32: "wifi_sar-galith.hex" > If this case happens, i would suggest to return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of "wifi_sar- […] I didn't follow wifi sar cbfs file closely already but I found that config - CONFIG_WIFI_SAR_CBFS_FILEPATH is defined as "" in [1]. And it looks like the config above will be used as wifi_sar_defaults.hex path [2]. In the end, WIFI_SAR_CBFS_DEFAULT_FILENAME is defined as wifi_sar_defaults.hex in sar.h. As a result, if we return WIFI_SAR_CBFS_DEFAULT_FILENAME then there will be no sar table be returned? On the other hand, if there is no SKU which don't need any SAR table then we should not define CONFIG_WIFI_SAR_CBFS_FILEPATH to "" but wifi_sar-galith.hex in this case. [1] https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/… [2] https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/he… -- To view, visit https://review.coreboot.org/c/coreboot/+/58734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Gerrit-Change-Number: 58734 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Marco Chen <marcochen(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 11:30:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Add two thermal sensor setting
by Chen Wisley (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/58970 to review the following change. Change subject: mb/google/brya/var/redrix: Add two thermal sensor setting ...................................................................... mb/google/brya/var/redrix: Add two thermal sensor setting Redrix has 4 thermal sensors, so add the missing sensors settings. BUG=b:200134784 TEST=build and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58970/1 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 0ed6c52..370957f 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -84,13 +84,18 @@ chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[1].desc" = ""SOC"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""5V regulator"" + # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 55, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 45, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 51, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 51, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 51, 5000), }" register "controls.power_limits" = "{ .pl1 = { -- To view, visit https://review.coreboot.org/c/coreboot/+/58970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 Gerrit-Change-Number: 58970 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
by Zhuohao Lee (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Henry Sun, Frank Chu, Karthik Ramasubramanian. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58734 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/dedede/variants/galtic/variant.c: https://review.coreboot.org/c/coreboot/+/58734/comment/7fbca72b_b3583e46 PS5, Line 32: "wifi_sar-galith.hex" If this case happens, i would suggest to return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of "wifi_sar-galith.hex" -- To view, visit https://review.coreboot.org/c/coreboot/+/58734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Gerrit-Change-Number: 58734 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 10:35:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Werner Zeh (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Patrick Rudolph, Felix Held. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 47: (1 comment) File src/soc/intel/elkhartlake/Kconfig: https://review.coreboot.org/c/coreboot/+/55367/comment/de4ff227_14201b2c PS47, Line 211: config PSE_FW_FILE_SIZE : hex "Memory buffer (KiB) for PSE FW image" : default 0x200 : help : It is recommended to allocate at least 512 KiB for PSE FW : : config PSE_CONFIG_BUFFER_SIZE : hex "Memory buffer (KiB) for PSE config data" : default 0x100 : help : It is recommended to allocate at least 256 KiB for PSE config : data (FSP will append PSE config data to memory region right : after PSE FW memory region) Make these dependent on "PSE_IMAGE so that they disappear if the PSE is disabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 47 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 10:15:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021