coreboot-gerrit November 2021

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Change in coreboot[master]: spd: Add lp5 directory with empty memory_parts file
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58928 ) Change subject: spd: Add lp5 directory with empty memory_parts file ...................................................................... spd: Add lp5 directory with empty memory_parts file Add spd/lp5/memory_parts.json with an empty parts list, then run spd_gen to generate the manifests and empty SPD. Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: I0314314130a1ccc58fb5a0416b110e7a86338fd0 Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58928 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A spd/lp5/memory_parts.json A spd/lp5/platforms_manifest.generated.txt A spd/lp5/set-0/parts_spd_manifest.generated.txt A spd/lp5/set-0/spd-empty.hex 4 files changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json new file mode 100644 index 0000000..ef8d9f9 --- /dev/null +++ b/spd/lp5/memory_parts.json @@ -0,0 +1,3 @@ +{ + "parts": [] +} diff --git a/spd/lp5/platforms_manifest.generated.txt b/spd/lp5/platforms_manifest.generated.txt new file mode 100644 index 0000000..95f5dbb --- /dev/null +++ b/spd/lp5/platforms_manifest.generated.txt @@ -0,0 +1,4 @@ +# Generated by: +# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 + +ADL,set-0 diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt new file mode 100644 index 0000000..ae22757 --- /dev/null +++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt @@ -0,0 +1,3 @@ +# Generated by: +# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 + diff --git a/spd/lp5/set-0/spd-empty.hex b/spd/lp5/set-0/spd-empty.hex new file mode 100644 index 0000000..1a5be53 --- /dev/null +++ b/spd/lp5/set-0/spd-empty.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0314314130a1ccc58fb5a0416b110e7a86338fd0 Gerrit-Change-Number: 58928 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/taeko: Update the FIVR configurations
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58943 ) Change subject: mb/google/taeko: Update the FIVR configurations ...................................................................... mb/google/taeko: Update the FIVR configurations This patch sets the enable the external voltage rails since taeko board have V1p05 and Vnn bypass rails. BRANCH=None BUG=b:204832954 TEST=FW_NAME=Check in FSP log and run PLT test Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 4398fa5..8ad5479 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -41,6 +41,19 @@ end end chip soc/intel/alderlake + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "SaGv" = "SaGv_Enabled" -- To view, visit https://review.coreboot.org/c/coreboot/+/58943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9 Gerrit-Change-Number: 58943 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/felwinter: Correct typeC EC mux port
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58930 ) Change subject: mb/google/brya/var/felwinter: Correct typeC EC mux port ...................................................................... mb/google/brya/var/felwinter: Correct typeC EC mux port Type C port2 uses EC mux port0 as per schematics. BUG=b:204230406 TEST=No error message in depthahrge. update_port_state: port C2: get_usb_pd_mux_info failed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58930 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 0fa2e61..9bd7ab5 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -123,10 +123,9 @@ end end device ref pch_espi on - #TBD, felwinter remove typeC port0 chip ec/google/chromeec use conn1 as mux_conn[1] - use conn2 as mux_conn[2] + use conn2 as mux_conn[0] device pnp 0c09.0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/58930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a Gerrit-Change-Number: 58930 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Change the flag value to type bool
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58942 ) Change subject: amdfwtool: Change the flag value to type bool ...................................................................... amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 33 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 395ce12..049755b 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -638,7 +638,7 @@ * 1st-level cookie may indicate level 1 or flattened. If the caller * passes a pointer to a 2nd-level table, then assume not flat. */ - if (cb_config->multi_level == 0) + if (!cb_config->multi_level) level = PSP_BOTH; else if (cookie == PSPL2_COOKIE) level = PSP_LVL2; @@ -739,7 +739,7 @@ fill_dir_header(pspdir, count, cookie, ctx); } -static void *new_bios_dir(context *ctx, int multi) +static void *new_bios_dir(context *ctx, bool multi) { void *ptr; @@ -822,7 +822,7 @@ * 1st-level cookie may indicate level 1 or flattened. If the caller * passes a pointer to a 2nd-level table, then assume not flat. */ - if (cb_config->multi_level == 0) + if (!cb_config->multi_level) level = BDT_BOTH; else if (cookie == BDT2_COOKIE) level = BDT_LVL2; @@ -1293,12 +1293,12 @@ int debug = 0; int list_deps = 0; - cb_config.have_whitelist = 0; - cb_config.unlock_secure = 0; - cb_config.use_secureos = 0; - cb_config.load_mp2_fw = 0; - cb_config.s0i3 = 0; - cb_config.multi_level = 0; + cb_config.have_whitelist = false; + cb_config.unlock_secure = false; + cb_config.use_secureos = false; + cb_config.load_mp2_fw = false; + cb_config.s0i3 = false; + cb_config.multi_level = false; while (1) { int optindex = 0; @@ -1322,24 +1322,24 @@ sub = instance = 0; break; case AMDFW_OPT_COMBO: - comboable = 1; + comboable = true; break; case AMDFW_OPT_MULTILEVEL: - cb_config.multi_level = 1; + cb_config.multi_level = true; break; case AMDFW_OPT_UNLOCK: register_fw_token_unlock(); - cb_config.unlock_secure = 1; + cb_config.unlock_secure = true; sub = instance = 0; break; case AMDFW_OPT_USE_PSPSECUREOS: - cb_config.use_secureos = 1; + cb_config.use_secureos = true; break; case AMDFW_OPT_INSTANCE: instance = strtoul(optarg, &tmp, 16); break; case AMDFW_OPT_LOAD_MP2FW: - cb_config.load_mp2_fw = 1; + cb_config.load_mp2_fw = true; break; case AMDFW_OPT_NVRAM: register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); @@ -1398,12 +1398,12 @@ sub = instance = 0; break; case AMDFW_OPT_LOAD_S0I3: - cb_config.s0i3 = 1; + cb_config.s0i3 = true; break; case AMDFW_OPT_WHITELIST: register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); sub = instance = 0; - cb_config.have_whitelist = 1; + cb_config.have_whitelist = true; break; case AMDFW_OPT_VERSTAGE: register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); @@ -1603,7 +1603,6 @@ psp_directory_table *pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir2, NULL, amd_psp_fw_table, PSPL2_COOKIE, &cb_config); - pspdir = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir, pspdir2, amd_psp_fw_table, PSP_COOKIE, &cb_config); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index b37503e..a7ac7c1 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -4,6 +4,7 @@ #define _AMD_FW_TOOL_H_ #include <stdint.h> +#include <stdbool.h> typedef enum _amd_fw_type { AMD_FW_PSP_PUBKEY = 0, @@ -220,12 +221,12 @@ } amd_fw_entry; typedef struct _amd_cb_config { - uint8_t have_whitelist; - uint8_t unlock_secure; - uint8_t use_secureos; - uint8_t load_mp2_fw; - uint8_t multi_level; - uint8_t s0i3; + bool have_whitelist; + bool unlock_secure; + bool use_secureos; + bool load_mp2_fw; + bool multi_level; + bool s0i3; } amd_cb_config; void register_fw_fuse(char *str); diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 784ee67..8f93183 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -108,7 +108,7 @@ uint8_t subprog; if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { - if (cb_config->have_whitelist == 1) { + if (cb_config->have_whitelist) { fw_type = AMD_FW_PSP_BOOTLOADER_AB; subprog = 0; } else { @@ -160,14 +160,14 @@ fw_type = AMD_FW_PSP_SMU_FIRMWARE2; subprog = 2; } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { - if (cb_config->unlock_secure == 1) { + if (cb_config->unlock_secure) { fw_type = AMD_FW_PSP_SECURED_DEBUG; subprog = 0; } else { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { - if (cb_config->unlock_secure == 1) { + if (cb_config->unlock_secure) { fw_type = AMD_DEBUG_UNLOCK; subprog = 0; } else { @@ -198,7 +198,7 @@ fw_type = AMD_ABL7; subprog = 0; } else if (strcmp(fw_name, "PSPSECUREOS_FILE") == 0) { - if (cb_config->use_secureos == 1) { + if (cb_config->use_secureos) { fw_type = AMD_FW_PSP_SECURED_OS; subprog = 0; } else { @@ -231,21 +231,21 @@ fw_type = AMD_SEC_GASKET; subprog = 2; } else if (strcmp(fw_name, "PSP_MP2FW0_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { + if (cb_config->load_mp2_fw) { fw_type = AMD_MP2_FW; subprog = 0; } else { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { + if (cb_config->load_mp2_fw) { fw_type = AMD_MP2_FW; subprog = 1; } else { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { + if (cb_config->load_mp2_fw) { fw_type = AMD_MP2_FW; subprog = 2; } else { @@ -255,7 +255,7 @@ fw_type = AMD_DRIVER_ENTRIES; subprog = 0; } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { - if (cb_config->s0i3 == 1) { + if (cb_config->s0i3) { fw_type = AMD_S0I3_DRIVER; subprog = 0; } else { @@ -295,7 +295,7 @@ fw_type = AMD_RPMC_NVRAM; subprog = 0; } else if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) { - if (cb_config->have_whitelist == 0) { + if (!cb_config->have_whitelist) { fw_type = AMD_FW_PSP_BOOTLOADER_AB; subprog = 0; } else { @@ -372,7 +372,7 @@ subprog = 0; instance = 0; } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { + if (cb_config->load_mp2_fw) { fw_type = AMD_BIOS_MP2_CFG; subprog = 0; } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/58942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Gerrit-Change-Number: 58942 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Fix the parameter point to NULL instead of integer
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58941 ) Change subject: amdfwtool: Fix the parameter point to NULL instead of integer ...................................................................... amdfwtool: Fix the parameter point to NULL instead of integer Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index d088179..395ce12 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1601,7 +1601,7 @@ if (cb_config.multi_level) { /* Do 2nd PSP directory followed by 1st */ psp_directory_table *pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); - integrate_psp_firmwares(&ctx, pspdir2, 0, + integrate_psp_firmwares(&ctx, pspdir2, NULL, amd_psp_fw_table, PSPL2_COOKIE, &cb_config); pspdir = new_psp_dir(&ctx, cb_config.multi_level); @@ -1610,7 +1610,7 @@ } else { /* flat: PSP 1 cookie and no pointer to 2nd table */ pspdir = new_psp_dir(&ctx, cb_config.multi_level); - integrate_psp_firmwares(&ctx, pspdir, 0, + integrate_psp_firmwares(&ctx, pspdir, NULL, amd_psp_fw_table, PSP_COOKIE, &cb_config); } @@ -1637,7 +1637,7 @@ /* Do 2nd level BIOS directory followed by 1st */ bios_directory_table *biosdir2 = new_bios_dir(&ctx, cb_config.multi_level); - integrate_bios_firmwares(&ctx, biosdir2, 0, + integrate_bios_firmwares(&ctx, biosdir2, NULL, amd_bios_table, BDT2_COOKIE, &cb_config); biosdir = new_bios_dir(&ctx, cb_config.multi_level); @@ -1646,7 +1646,7 @@ } else { /* flat: BDT1 cookie and no pointer to 2nd table */ biosdir = new_bios_dir(&ctx, cb_config.multi_level); - integrate_bios_firmwares(&ctx, biosdir, 0, + integrate_bios_firmwares(&ctx, biosdir, NULL, amd_bios_table, BDT1_COOKIE, &cb_config); } switch (soc_id) { -- To view, visit https://review.coreboot.org/c/coreboot/+/58941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4 Gerrit-Change-Number: 58941 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Change the definition of level to a bitwise form
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58765 ) Change subject: amdfwtool: Change the definition of level to a bitwise form ...................................................................... amdfwtool: Change the definition of level to a bitwise form Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.h 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index d7f0f5d..b37503e 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -182,8 +182,8 @@ bios_directory_entry entries[]; } bios_directory_table; -#define BDT_LVL1 0x1 -#define BDT_LVL2 0x2 +#define BDT_LVL1 (1 << 0) +#define BDT_LVL2 (1 << 1) #define BDT_BOTH (BDT_LVL1 | BDT_LVL2) typedef struct _amd_bios_entry { amd_bios_type type; @@ -208,8 +208,8 @@ #define BDT1_COOKIE 0x44484224 /* 'DHB$ */ #define BDT2_COOKIE 0x324c4224 /* '2LB$ */ -#define PSP_LVL1 0x1 -#define PSP_LVL2 0x2 +#define PSP_LVL1 (1 << 0) +#define PSP_LVL2 (1 << 1) #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) typedef struct _amd_fw_entry { amd_fw_type type; -- To view, visit https://review.coreboot.org/c/coreboot/+/58765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061 Gerrit-Change-Number: 58765 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Pack out-of-bounds check into a function and move
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Zheng Bao. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58764 ) Change subject: amdfwtool: Pack out-of-bounds check into a function and move ...................................................................... Patch Set 3: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/58764/comment/d3e31717_3cbcb8f7 PS3, Line 738: if (count > MAX_PSP_ENTRIES) { `count` can be higher here than in line 671, so with after this change, we'd not see errors where we see them now. -- To view, visit https://review.coreboot.org/c/coreboot/+/58764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Gerrit-Change-Number: 58764 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 05 Nov 2021 12:55:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/lib: Support fallback option for fw_config
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Ravishankar Sarawadi, Subrata Banik, Julius Werner, Nick Vaccaro, Raj Astekar, Srinidhi N Kaushik. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58833 ) Change subject: src/lib: Support fallback option for fw_config ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58833/comment/ecab93f9_3f80296e PS7, Line 7: src/lib: Support fallback option for fw_config : : To support both non-chrome EC platform and chrome EC platform in : single coreboot binary, need to support fallback option. : Make reading fw_config from CBI and support other options as : fallback options and support backward compatiblity to support only one : option as before. Sorry, but this confuses readers more than it helps explain what's going on here. How about: src/lib/fw_config: Change fw_config sources priority Request fw_config values from various sources (as enabled via Kconfig) until a valid value has been read. With this change, Chrome EC CBI takes precedence over CBFS fw_config. File src/Kconfig: https://review.coreboot.org/c/coreboot/+/58833/comment/65433007_bfae7c90 PS7, Line 408: config FW_CONFIG_SOURCE_CBFS Why move this? -- To view, visit https://review.coreboot.org/c/coreboot/+/58833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff Gerrit-Change-Number: 58833 Gerrit-PatchSet: 7 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 12:51:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/herobrine: Initialize USB by calling SOC method
by Ravi Kumar Bokka (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56093 ) Change subject: mb/google/herobrine: Initialize USB by calling SOC method ...................................................................... Patch Set 33: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56093/comment/b819fe9c_d5061777 PS28, Line 7: herobrine: Add support for USB initialization > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/56093/comment/06a58968_e8fc2c1d PS28, Line 9: Initializing USB controller driver. > … by calling `setup_usb_host0()` from SOC code. Done https://review.coreboot.org/c/coreboot/+/56093/comment/54b76d26_72a22383 PS28, Line 9: Initializing > Initialize Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Gerrit-Change-Number: 56093 Gerrit-PatchSet: 33 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Nov 2021 12:43:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/acpi/gpio.md: Update implementation details
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58933 ) Change subject: Documentation/acpi/gpio.md: Update implementation details ...................................................................... Documentation/acpi/gpio.md: Update implementation details The weak functions were removed in bce7458 "acpi/acpigen.c: Remove weak gpio definition". Change-Id: Ia6e51698d6209fbf4f59b7fbc988a1aa696e366f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58933 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M Documentation/acpi/gpio.md 1 file changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/Documentation/acpi/gpio.md b/Documentation/acpi/gpio.md index 470a55f..2d38f99 100644 --- a/Documentation/acpi/gpio.md +++ b/Documentation/acpi/gpio.md @@ -84,15 +84,6 @@ ## Implementation Details -ACPI library in coreboot will provide weak definitions for all the -above functions with error messages indicating that these functions -are being used. This allows drivers to conditionally make use of GPIOs -based on device-tree entries or any other config option. It is -recommended that the SoC code in coreboot should provide -implementations of all the above functions generating ACPI AML code -irrespective of them being used in any driver. This allows mainboards -to use any drivers and take advantage of this common infrastructure. - Platforms are restricted to using Local5, Local6 and Local7 variables only in implementations of the above functions. Any AML methods called by the above functions do not have any such restrictions on use of -- To view, visit https://review.coreboot.org/c/coreboot/+/58933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6e51698d6209fbf4f59b7fbc988a1aa696e366f Gerrit-Change-Number: 58933 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021