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Change subject: mb/google/guybrush: Define ACPI Power Resources for FPMCU
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File src/mainboard/google/guybrush/variants/guybrush/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/58705/comment/6535a6ea_6665266e
PS4, Line 178: enable_delay_ms
Actually, do we also want enable_off_delay_ms = 200?
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Change subject: mb/google/guybrush: Define ACPI Power Resources for FPMCU
......................................................................
Patch Set 4: Code-Review+2
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Change subject: amdfwtool: Pack out-of-bounds check into a function and move
......................................................................
Patch Set 3:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/58764/comment/2bcf05e4_0f56d9fe
PS3, Line 738: if (count > MAX_PSP_ENTRIES) {
> `count` can be higher here than in line 671, so with after this change, we'd not see errors where we […]
But in assert_fw_entry, the comparison is change to ">=". I assume the effect are the same.
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Change subject: [RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS()
......................................................................
Patch Set 5:
(4 comments)
File src/vendorcode/google/chromeos/chromeos.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132402):
https://review.coreboot.org/c/coreboot/+/58899/comment/9f501a35_65284148
PS5, Line 103: #define DECLARE_CROS_GPIOS(x) \
Macros with flow control statements should be avoided
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132402):
https://review.coreboot.org/c/coreboot/+/58899/comment/5c13a70f_3c99b046
PS5, Line 104: const struct cros_gpio *variant_cros_gpios(size_t *num) \
please, no space before tabs
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132402):
https://review.coreboot.org/c/coreboot/+/58899/comment/4a67c0a8_791b5ba8
PS5, Line 110: #define DECLARE_WEAK_CROS_GPIOS(x) \
Macros with flow control statements should be avoided
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132402):
https://review.coreboot.org/c/coreboot/+/58899/comment/40e07f4c_79d1342e
PS5, Line 111: const struct cros_gpio *__weak variant_cros_gpios(size_t *num) \
please, no space before tabs
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Change subject: ChromeOS: Add legacy mainboard_ec_running_ro()
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS2:
> hm, motivation is good, but is there a way to do it without adding another weak function?
I'll look into it, but would probably need a new Kconfig.
File src/vendorcode/google/chromeos/gnvs.c:
https://review.coreboot.org/c/coreboot/+/58896/comment/41fdbcd3_420b6946
PS2, Line 36: )
> `void` here, also we usually keep __weak before the return type e.g. […]
Done
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Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58798/comment/86088e5d_58c8bc35
PS9, Line 9: Linux 5.13 or later
> Interesting. Do you have a commit where this got removed from Linux 5. […]
c6da62a219d0 ("thunderbolt: Add support for native USB4 _OSC")
With this commit the TBT driver attempts to *only* use software CM because native USB4 control is advertised.
(Support is initially detected at `acpi_bus_osc_negotiate_{platform,usb}_control()` in `drivers/acpi/bus.c`.)
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Julius Werner, Alexander Couzens, Andrey Petrov, Yu-Ping Wu, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs
......................................................................
[WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs
It should be optional to protect MRC_CACHE without
CHROMEOS so MRC_SETTINGS_PROTECT cannot be enforced
from soc/.
This change selects MRC_SETTINGS_PROTECT also for older
platforms when CHROMEOS is selected.
If a board does not implement get_write_protect_state()
MRC_SETTINGS_PROTECT should not be selected since the
related SPI flash pages will not get protected.
Currently, such real implementations may or may not be
guarded with CONFIG(CHROMEOS) and the protection is
only expected to work after followup works.
Change-Id: I8db0394645df1917b686339fa79432ccfc6960a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/drivers/mrc_cache/mrc_cache.c
M src/ec/lenovo/h8/vboot.c
M src/mainboard/amd/majolica/chromeos.c
M src/mainboard/google/foster/chromeos.c
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/galileo/vboot.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/jasperlake_rvp/chromeos.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/tglrvp/chromeos.c
M src/mainboard/intel/wtm2/chromeos.c
M src/security/vboot/bootmode.c
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/tigerlake/Kconfig
M src/vendorcode/google/chromeos/Kconfig
24 files changed, 4 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/58968/2
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Karthik Ramasubramanian,
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Change subject: [RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS()
......................................................................
[RFC] ChromeOS: Add DECLARE_x_CROS_GPIOS()
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/emulation/qemu-q35/chromeos.c
M src/mainboard/google/auron/chromeos.c
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/dedede/variants/baseboard/gpio.c
M src/mainboard/google/deltaur/variants/baseboard/gpio.c
M src/mainboard/google/drallion/variants/drallion/gpio.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/variants/baseboard/gpio.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/guybrush/chromeos.c
M src/mainboard/google/hatch/variants/baseboard/gpio.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/link/chromeos.c
M src/mainboard/google/octopus/variants/baseboard/gpio.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/poppy/variants/baseboard/gpio.c
M src/mainboard/google/rambi/chromeos.c
M src/mainboard/google/reef/variants/baseboard/gpio.c
M src/mainboard/google/reef/variants/coral/gpio.c
M src/mainboard/google/sarien/variants/arcada/gpio.c
M src/mainboard/google/sarien/variants/sarien/gpio.c
M src/mainboard/google/slippy/chromeos.c
M src/mainboard/google/stout/chromeos.c
M src/mainboard/google/volteer/variants/baseboard/gpio.c
M src/mainboard/google/zork/chromeos.c
M src/mainboard/intel/adlrvp/gpio.c
M src/mainboard/intel/adlrvp/gpio_m.c
M src/mainboard/intel/baskingridge/chromeos.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/emeraldlake2/chromeos.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c
M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kunimitsu/chromeos.c
M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
M src/mainboard/intel/strago/chromeos.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
M src/mainboard/intel/wtm2/chromeos.c
M src/mainboard/samsung/lumpy/chromeos.c
M src/mainboard/samsung/stumpy/chromeos.c
M src/vendorcode/google/chromeos/chromeos.h
49 files changed, 62 insertions(+), 240 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/58899/5
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