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Change in edk2[coreboot-stable202108]: UefiPayloadPkg: Increase FV size to 8MB
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Patrick Rudolph, Matt DeVillier, Paul Menzel, Marvin Drees. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/edk2/+/58630 ) Change subject: UefiPayloadPkg: Increase FV size to 8MB ...................................................................... Patch Set 4: -Code-Review -- To view, visit https://review.coreboot.org/c/edk2/+/58630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I6b757f73fe4e90282b4bfb84469545ab1af9d1bb Gerrit-Change-Number: 58630 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 15:58:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in edk2[coreboot-stable202108]: UefiPayloadPkg: Increase FV size to 8MB
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Patrick Rudolph, Matt DeVillier, Paul Menzel, Marvin Drees. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/edk2/+/58630 ) Change subject: UefiPayloadPkg: Increase FV size to 8MB ...................................................................... Patch Set 4: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/edk2/+/58630/comment/517aab3b_be00b985 PS2, Line 7: UefiPayloadPkg: Increase FV size > … to X MB Done Patchset: PS1: > Patrick/Marvin: is this increase sufficient for all the current/near-term features in 9elements' for […] It's a lot. If they want more, they can add their own commit, but no need to wait. -- To view, visit https://review.coreboot.org/c/edk2/+/58630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I6b757f73fe4e90282b4bfb84469545ab1af9d1bb Gerrit-Change-Number: 58630 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 15:51:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in edk2[coreboot-stable202108]: UefiPayloadPkg: Increase FV size to 8MB
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Patrick Rudolph, Matt DeVillier, Marvin Drees. Hello build bot (Jenkins), Patrick Rudolph, Marvin Drees, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/edk2/+/58630 to look at the new patch set (#4). Change subject: UefiPayloadPkg: Increase FV size to 8MB ...................................................................... UefiPayloadPkg: Increase FV size to 8MB The following commits need additional space. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I6b757f73fe4e90282b4bfb84469545ab1af9d1bb --- M UefiPayloadPkg/UefiPayloadPkg.fdf 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/edk2 refs/changes/30/58630/4 -- To view, visit https://review.coreboot.org/c/edk2/+/58630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: edk2 Gerrit-Branch: coreboot-stable202108 Gerrit-Change-Id: I6b757f73fe4e90282b4bfb84469545ab1af9d1bb Gerrit-Change-Number: 58630 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google,intel: Fix indirect include bootmode.h
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58921 ) Change subject: mb/google,intel: Fix indirect include bootmode.h ...................................................................... mb/google,intel: Fix indirect include bootmode.h Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/amd/majolica/chromeos.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/hatch/variants/baseboard/mainboard.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/ramstage.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c 36 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Felix Held: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c index c73e047..e5f3b5c 100644 --- a/src/mainboard/amd/majolica/chromeos.c +++ b/src/mainboard/amd/majolica/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index 1af2e02..630874c 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 50eeddc..2274ff7 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/chromeos.h> diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index add7346..e0a13b8 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index b88862c..14efdc3 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/mmio.h> #include <gpio.h> diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index fb904cc..0d75ac3 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 9d3929e..dbdb273 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c index 09e0987..caa99a9 100644 --- a/src/mainboard/google/deltaur/variants/deltan/memory.c +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <gpio.h> #include <soc/romstage.h> +#include <string.h> static const struct mb_cfg baseboard_memcfg = { .type = MEM_TYPE_DDR4, diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index d92ebb1..e3a9cd3 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 11931c6..73eae78 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index a74c2f7..a9456e4 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <baseboard/variants.h> diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 0945b9c..307fadd 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <chip.h> #include <console/console.h> #include <delay.h> diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 6a1f0b4..acd4cd6 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index df99e64..6cd48ea 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -3,6 +3,7 @@ #include <amdblocks/spi.h> #include <baseboard/gpio.h> #include <boardid.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index ee54ade..354d839 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index d641405..c6c87dc 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <bootmode.h> #include <chip.h> #include <console/console.h> #include <delay.h> diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index cf59636..5cfe9df 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index b85f976..a386dd6 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 03d3b4f..d0ceabc 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 5dd1e98..c9b91ad 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 94d76b9..a45ccdd 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index f49b639..3dc9f19 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index abd50c5..5f87821 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index b581b90..cfb55a7 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index 244b942..85807a1 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index f93b361..93f1aa3a2 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <console/console.h> #include <soc/romstage.h> #include "board_id.h" diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 136fa45..22902bd 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -8,6 +8,7 @@ #include <soc/gpio_soc_defs.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <string.h> #include <drivers/intel/dptf/chip.h> #include "board_id.h" #include <intelblocks/power_limit.h> diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 5fb7922..1e02e3d 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 5944406..7878a2a 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index c98c4f8..8a8bc42 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index c59fac8..320f92a 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 270c84d..df01242 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> #include <gpio.h> diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 3b8725f..3a99e25 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c index 35a54a8..052191f 100644 --- a/src/mainboard/intel/shadowmountain/chromeos.c +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index f01f7f1..c0ce968 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 7da61be..cb9af47 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/58921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Gerrit-Change-Number: 58921 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google,intel: Fix indirect include bootmode.h
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nick Vaccaro, Kyösti Mälkki. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58921 ) Change subject: mb/google,intel: Fix indirect include bootmode.h ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58921/comment/0913aabb_38801d4f PS3, Line 7: mb/google,intel: Fix indirect includes : : We have <baseboard/variants.h> that currently pulls : in <vc/google/chromeos/chromeos.h>, addressing that : triggered some errors. > Better? I guess that's how I came across this originally on some file and fixed treewide. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/58921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Gerrit-Change-Number: 58921 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 15:39:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google,intel: Fix indirect include bootmode.h
by Patrick Georgi (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nick Vaccaro. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58921 ) Change subject: mb/google,intel: Fix indirect include bootmode.h ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Gerrit-Change-Number: 58921 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Nov 2021 15:39:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu-i440fx: Refactor `fw_cfg_max_cpus()`
by Felix Held (Code Review) 05 Nov '21

05 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58918 ) Change subject: mb/emulation/qemu-i440fx: Refactor `fw_cfg_max_cpus()` ...................................................................... mb/emulation/qemu-i440fx: Refactor `fw_cfg_max_cpus()` Return 0 instead of -1 in case of error. Both values indicate an error has happened. Adapt `cpu_bus_scan()` accordingly. Change-Id: I0f83fdc41c20ed3aae80829432fc84024f5b9b47 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58918 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/northbridge.c 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 01be2c3..3206e4c 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -133,7 +133,7 @@ unsigned short max_cpus; if (!fw_cfg_present()) - return -1; + return 0; fw_cfg_get(FW_CFG_MAX_CPUS, &max_cpus, sizeof(max_cpus)); return max_cpus; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index d041b0c..9785a3a 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -265,11 +265,11 @@ static void cpu_bus_scan(struct device *bus) { - int max_cpus = fw_cfg_max_cpus(); + unsigned int max_cpus = fw_cfg_max_cpus(); struct device *cpu; int i; - if (max_cpus < 0) + if (max_cpus == 0) return; /* * Do not install more CPUs than supported by coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/58918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f83fdc41c20ed3aae80829432fc84024f5b9b47 Gerrit-Change-Number: 58918 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel: Use unsigned types in `get_cpu_count()`
by Felix Held (Code Review) 05 Nov '21

05 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58917 ) Change subject: cpu/intel: Use unsigned types in `get_cpu_count()` ...................................................................... cpu/intel: Use unsigned types in `get_cpu_count()` Change-Id: Id95e45a3eba384a61c02016b7663ec71c3ae1865 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58917 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c 4 files changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2ab77b3..d4f3587 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -588,8 +588,8 @@ static int get_cpu_count(void) { msr_t msr; - int num_threads; - int num_cores; + unsigned int num_threads; + unsigned int num_cores; msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 9a1fc42..bc53214 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -23,7 +23,7 @@ static int get_cpu_count(void) { const struct cpuid_result cpuid1 = cpuid(1); - const char cores = (cpuid1.ebx >> 16) & 0xf; + const unsigned int cores = (cpuid1.ebx >> 16) & 0xf; printk(BIOS_DEBUG, "CPU has %u cores.\n", cores); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 30519c0..e77f9aa 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -124,8 +124,8 @@ static int get_cpu_count(void) { msr_t msr; - int num_threads; - int num_cores; + unsigned int num_threads; + unsigned int num_cores; msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d240f53..9de6b38 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -380,8 +380,8 @@ static int get_cpu_count(void) { msr_t msr; - int num_threads; - int num_cores; + unsigned int num_threads; + unsigned int num_cores; msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; -- To view, visit https://review.coreboot.org/c/coreboot/+/58917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e45a3eba384a61c02016b7663ec71c3ae1865 Gerrit-Change-Number: 58917 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/pci_rom: Add vga_oprom_preload
by Rob Barnes (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56581 ) Change subject: device/pci_rom: Add vga_oprom_preload ...................................................................... Patch Set 9: Code-Review+1 (1 comment) File src/device/pci_rom.c: https://review.coreboot.org/c/coreboot/+/56581/comment/48b78cd6_99793361 PS9, Line 28: printk(BIOS_DEBUG, "Preloading VGA ROM\n"); nit: printing name here would be helpful for debugging. -- To view, visit https://review.coreboot.org/c/coreboot/+/56581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb54fe3a942e9507ff6f1173ba5620a8f4ce6549 Gerrit-Change-Number: 56581 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 05 Nov 2021 15:20:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu,soc/amd/common/block/cpu: Add preload_microcode
by Rob Barnes (Code Review) 05 Nov '21

05 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58963 ) Change subject: src/cpu,soc/amd/common/block/cpu: Add preload_microcode ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/amd/common/block/cpu/update_microcode.c: https://review.coreboot.org/c/coreboot/+/58963/comment/f77185eb_7353c259 PS1, Line 132: printk(BIOS_DEBUG, "Preloading microcode\n"); nit: Printing CPU_MICROCODE_BLOB_NAME here would be helpful for debugging. -- To view, visit https://review.coreboot.org/c/coreboot/+/58963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Gerrit-Change-Number: 58963 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Nov 2021 15:19:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021