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Change subject: mb/google/brya/var/brask: Configurate the GPIOs of LAN
......................................................................
Patch Set 6:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58105/comment/983dabd4_8c9cec67
PS6, Line 7: Configurate
Configure
https://review.coreboot.org/c/coreboot/+/58105/comment/fb80bab2_2fb3a009
PS6, Line 9: Copy the default configuration from Puff.
: Update the 'stop_gpio' to GPP_H22.
: Remove 'wake'. ("WAKE#" is not a GPIO pin.)
Please format this as a list.
https://review.coreboot.org/c/coreboot/+/58105/comment/8c49ab63_e2e37770
PS6, Line 15: Build Pass
Maybe note down the command.
https://review.coreboot.org/c/coreboot/+/58105/comment/7e35b2a1_5c118821
PS6, Line 15: Pass
pass
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Change subject: drivers/i2c/tpm: Fix blank default statement
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Patch Set 1: Code-Review+2
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Change subject: drivers/net/r8168: Add support for Realtek RT8125
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59086/comment/6fdb8da2_48bc2616
PS7, Line 14: TEST=emerge-brask coreboot chromeos-bootimage
> On what device? What didn’t work before, and what works now?
Oh, google/brask. Still the second questions remains.
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Change subject: drivers/net/r8168: Add support for Realtek RT8125
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59086/comment/a930978b_552d3c5b
PS7, Line 9: The Realtek RT8168 and RT8125 have a similar programming
: interface, therefore add the PCI device ID for the RT8125
: into driver for support.
Please reflow for 75 characters per line.
https://review.coreboot.org/c/coreboot/+/59086/comment/e0333298_48c6f60b
PS7, Line 14: TEST=emerge-brask coreboot chromeos-bootimage
On what device? What didn’t work before, and what works now?
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/59086/comment/1d389fc8_3c696cf0
PS7, Line 1287: #define PCI_DEVICE_ID_REALTEK_8125 0x8125
Please sort them.
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Change subject: drivers/i2c/tpm: Fix blank default statement
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Patch Set 1: Code-Review+2
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Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM
......................................................................
Patch Set 4:
(2 comments)
File src/security/vboot/secdata_tpm.c:
https://review.coreboot.org/c/coreboot/+/59476/comment/5a133534_4b675ffe
PS3, Line 345: space
> better: spaces (plural)
Done
https://review.coreboot.org/c/coreboot/+/59476/comment/dfb6e098_0578bb01
PS3, Line 349: <=
> I think you want < here or you'll end up with 5 counters.
Done. Thanks for catching that.
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Hello build bot (Jenkins), Andrey Pronin, Raul Rangel, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59476
to look at the new patch set (#4).
Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM
......................................................................
src/security/vboot: Set up secure counter space in TPM NVRAM
High Definition (HD) protected content playback requires secure counters
that are updated at regular interval while the protected content is
playing. To support similar use-cases, define space for secure counters
in TPM NVRAM and initialize them. These counters are defined once during
the factory initialization stage. Also add a config item to enable these
secure counters only on the mainboard where they are required/used.
BUG=b:205261728
TEST=Build and boot to OS in guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM space.
tlcl_define_space: response is 0
tlcl_define_space: response is 0
tlcl_define_space: response is 0
tlcl_define_space: response is 0
On reboot if forced to redefine the space, it is identified as already
defined.
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/security/vboot/Kconfig
M src/security/vboot/antirollback.h
M src/security/vboot/secdata_tpm.c
3 files changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59476/4
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59260 )
Change subject: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/redrix/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59260/comment/567632ad_a46d09f6
PS3, Line 355: GPP_D16
> I am a bit confused, which other place are we exposing D16 to driver ?
See line 324, which generates a separate power resource. We have reference counting built in to the driver to accomodate the fact that multiple PRs will each reference the same GPIOs.
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