coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/system76/*: Disable IME by CMOS option
by Jeremy Soller (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Tim Crawford. Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57621 ) Change subject: mb/system76/*: Disable IME by CMOS option ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Gerrit-Change-Number: 57621 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 20:43:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Patrick Georgi (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Raul Rangel, Martin Roth, Tim Wawrzynczak, Julius Werner. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Well, what you have right now seems really fragile, if just shifting a few calls around here and the […] If we have a cheap way of detecting if prefetching is done, handling the buffer could remain outside the prefetch task. Rough draft: int handle_rdev_buffer(command, data) { if (!CONFIG(PREFETCH)) return 0; if (prefetch == active) { append_to_buffer(command, data); return 1; } else if (prefetch == done) { flush_buffer_to_rdev; prefetch = off; } return 0; } rdev_eraseat(...) { if (handle_rdev_buffer(...)) return; normal_eraseat_things... } rdev_writeat(...) { if (handle_rdev_buffer(...)) return; normal_writeat_things... } The only interaction the prefetch task has with this is that it needs to set prefetch to "active" before starting work and to "done" when done. There also needs to be a call to flush_buffer_to_rdev sometimes at the end of a stage in case there's still stuff lingering in the buffer (e.g. nobody tried to write to flash after prefetch ended). -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 20:01:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage
by Raul Rangel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 ) Change subject: soc/amd/cezanne/romstage: Call preload_ramstage ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/cezanne/fsp_m_params.c: https://review.coreboot.org/c/coreboot/+/58983/comment/0525082f_d3ae3b39 PS5, Line 181: preload_ramstage(); > Why here and why not in soc/amd/cezanne/romstage. […] I was hoping the comment would explain it :( We want FSP-M to be free'd from the CBFS buffer before calling this. -- To view, visit https://review.coreboot.org/c/coreboot/+/58983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51 Gerrit-Change-Number: 58983 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 20:00:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Raul Rangel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Julius Werner. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Well, what you have right now seems really fragile, if just shifting a few calls around here and the […] I agree we can look into other solutions, but can we keep it simple for now? I don't think the CBFS prefetch thread is the correct place for this to live though. It would have to be a new boot device that implements both RO and RW devices. This device can then keep a priority queue of `rdev` requests. It would then have to call out into the platform specific boot device to actually perform the work. The CBFS preload thread wouldn't need to change since it just uses `rdev_readat`. On the AMD platform we have 2 boot devices: RW: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… RO: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… We would need to devise a way to make the `delegator` boot device get handles to the `platform` boot devices. Right now the RO device implements `boot_device_ro`. We would need to implement some kind of new registration method that works with and without the `delegator` boot device. There is still the outstanding question of having `_preload` methods for the files. -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 19:59:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax
by Julius Werner (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Raul Rangel, Philipp Hug, Ron Minnich. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59546 ) Change subject: arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax ...................................................................... Patch Set 1: (2 comments) File src/arch/arm/include/armv4/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/59546/comment/8183773d_860f8724 PS1, Line 6: __always_inline Just `inline` is enough. __always_inline is weird and shouldn't be used without good reason. File src/arch/arm64/include/armv8/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/59546/comment/c505ce95_e0fc1398 PS1, Line 6: static __always_inline void cpu_relax(void) { } Maybe add a TODO comment that this should be implement via SEV/WFE if it's ever actually used? -- To view, visit https://review.coreboot.org/c/coreboot/+/59546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcb4546ceb2894eeb37589d0282b7e076d7a4747 Gerrit-Change-Number: 59546 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 19:56:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add a mutex
by Julius Werner (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Raul Rangel, Kyösti Mälkki, Rob Barnes, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 7: (3 comments) File src/include/mutex.h: https://review.coreboot.org/c/coreboot/+/59320/comment/2c10501b_59716225 PS7, Line 22: else if (CONFIG(COOP_MULTITASKING)) This should be (ENV_RAMSTAGE || ENV_ROMSTAGE) && CONFIG(COOP_MULTITASKING) Maybe we should create an ENV_COOP_MULTITASKING to encapsulate that? File src/include/mutex.h: https://review.coreboot.org/c/coreboot/+/59320/comment/900671c8_2033ed1c PS6, Line 32: } > Right spinlock worked by start with 1 and decrementing. […] Are you saying we should make ENV_STATE_SUPPORTS_SMP evaluate to 1 in x86 romstage, Kyösti? But why? The x86 SMP start-up code for the non-boot CPUs is only in ramstage, right? There's no point SMP-proofing anything as long as only one CPU is up. It's not really about where you can implement the spinlock, more about where the spinlock is necessary. (In that sense I think it should probably be changed to (ENV_RAMSTAGE || ENV_SMP) for x86, since postcar should also have no SMP yet, right?) File src/include/mutex.h: https://review.coreboot.org/c/coreboot/+/59320/comment/6dfe43a4_40c6b3f4 PS2, Line 11: void mutex_unlock(struct mutex *mutex); > Done Nothing in coreboot uses LTO, it's not an easy thing to support. There have been experimental attempts for a while, the latest I'm aware of is CB:40815. You can try checking with Jacob how far he got and what was missing if you're interested. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 19:54:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage
by Karthik Ramasubramanian (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 ) Change subject: soc/amd/cezanne/romstage: Call preload_ramstage ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/cezanne/fsp_m_params.c: https://review.coreboot.org/c/coreboot/+/58983/comment/f32e15f0_08cf78fc PS5, Line 181: preload_ramstage(); Why here and why not in soc/amd/cezanne/romstage.c as part of car_stage_entry between APOB preload and fsp_memory_init() -- To view, visit https://review.coreboot.org/c/coreboot/+/58983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51 Gerrit-Change-Number: 58983 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 19:50:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by Subrata Banik (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59509 ) Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/Kconfig: https://review.coreboot.org/c/coreboot/+/59509/comment/02bc521b_81aa1bca PS4, Line 7: config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using Thermal PCI device : for chipsets till Ice Lake PCH. : : config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using PMC PWRMBASE : for chipsets since Tiger Lake PCH. > Meh, looks like Kconfig doesn't like my idea... I'd simply use a preprocessor check inside `thermal. […] HI Eric and Angel, I have summarized my observation based on what happen when SoC user wrongly tries to select both the Kconfig(s). With below results, I believe our latest patchset doesn't require any more modification to prohibit user to make redundant selection of thermal Kconfig. Also, we have #error check in thermal.h to avoid unnecessary include of this header without proper Kconfig selection. Please share your thoughts ? For ADL: When I have selected both the Kconfig as below: (ideally it should be SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC) select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC Error as below: WARNING: unmet direct dependencies detected for SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC Depends on [n]: SOC_INTEL_COMMON [=y] && SOC_INTEL_COMMON_BLOCK [=y] && !SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV [=y] Selected by [y]: - CPU_SPECIFIC_OPTIONS [=y] && SOC_INTEL_ALDERLAKE [=y] *** ERROR: 1 warnings encountered, and warnings are errors. For CML: When I have selected both the Kconfig as below: (ideally it should be SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC Error as below: WARNING: unmet direct dependencies detected for SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC Depends on [n]: SOC_INTEL_COMMON [=y] && SOC_INTEL_COMMON_BLOCK [=y] && !SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV [=y] Selected by [y]: - CPU_SPECIFIC_OPTIONS [=y] && SOC_INTEL_CANNONLAKE_BASE [=y] *** ERROR: 1 warnings encountered, and warnings are errors. -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 19:42:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Julius Werner (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Raul Rangel, Patrick Georgi, Martin Roth, Tim Wawrzynczak. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > > it seems slightly odd to have a function for each file in CBFS you want to preload. […] Well, what you have right now seems really fragile, if just shifting a few calls around here and there can completely regress your performance. It would be nice to have something more robust that platforms can just turn on without having to manually fine-tune everything. I think Patrick's write buffer is a good idea. Would have to expand the CBFS prefetch thread a bit to become a full boot device worker thread. Of course this adds more complexity but so did the whole prefetching thing to begin with (and that's why we should also make sure that all of this stays optional and can be fully disabled without leaving any overhead behind). (As for error handling, there are only so many useful ways you can deal with a SPI write error... ignore, die(), reboot, go into recovery... that's it, probably. Could just have the caller store that preference as an enum value in the write buffer entry.) -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 19:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/romstage: Start loading APOB asynchronously
by Karthik Ramasubramanian (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59502 ) Change subject: soc/amd/cezanne/romstage: Start loading APOB asynchronously ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb993debaf67027d4cd57920bcfb78fb05b9e68b Gerrit-Change-Number: 59502 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 19:40:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021