coreboot-gerrit November 2021

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Change in coreboot[master]: arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax
by Raul Rangel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Philipp Hug, Julius Werner, Ron Minnich. Hello build bot (Jenkins), Philipp Hug, Julius Werner, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59546 to look at the new patch set (#2). Change subject: arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax ...................................................................... arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax The cpu_relax method is defined for x86. This CL adds a no-op method so that it can be used in common code. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ifcb4546ceb2894eeb37589d0282b7e076d7a4747 --- M src/arch/arm/include/armv4/arch/cpu.h M src/arch/arm/include/armv7/arch/cpu.h M src/arch/arm64/include/armv8/arch/cpu.h M src/arch/ppc64/include/arch/cpu.h M src/arch/riscv/include/arch/cpu.h 5 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/59546/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcb4546ceb2894eeb37589d0282b7e076d7a4747 Gerrit-Change-Number: 59546 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Julius Werner (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Raul Rangel, Patrick Georgi, Martin Roth, Tim Wawrzynczak. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > IMO, it needs to be at a lower layer. APOB prefetch (start_apob_cache_read) only uses fmap_locate_area_as_rdev, so making it call into cbfs gets a little strange... Come to think of it, ELOG also uses a raw region. Right, I didn't say CBFS, I just said it should be its own API rather than being integrated into rdev_writeat() under the hood. More like an outside wrapper around the rdev functions. > Now that it's decoupled we can in theory resize the thread stack size. That sounds dangerous, though. coreboot programmers make certain assumptions about how much stack usage is okay vs too much. It's not always obvious (and may change after the fact) whether a function you're writing may be called from a special worker thread or not. Detect stack overflows after the fact at runtime is also quite brittle and dangerous to rely on. I'd much rather we don't create new stack overflow hazards and instead optimize usage of the stacks we have by being frugal with the amount of threads we create. -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 21:37:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Move payload preload after ELOG init
by Karthik Ramasubramanian (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59503 ) Change subject: soc/amd/cezanne: Move payload preload after ELOG init ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/preload.c: https://review.coreboot.org/c/coreboot/+/59503/comment/411545f5_f19da647 PS2, Line 24: BS_DEV_INIT_CHIPS Is this the right Boot State? I can see that the elog_bs_init/elog_init is performed during BS_POST_DEVICE boot state? -- To view, visit https://review.coreboot.org/c/coreboot/+/59503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9baf43fab70f6a11d8a240e1dd94af70271c568 Gerrit-Change-Number: 59503 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 21:36:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage
by Karthik Ramasubramanian (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 ) Change subject: soc/amd/cezanne/romstage: Call preload_ramstage ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51 Gerrit-Change-Number: 58983 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 21:30:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage
by Karthik Ramasubramanian (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 ) Change subject: soc/amd/cezanne/romstage: Call preload_ramstage ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/cezanne/fsp_m_params.c: https://review.coreboot.org/c/coreboot/+/58983/comment/f23f1f03_37949dcf PS5, Line 181: preload_ramstage(); > I was hoping the comment would explain it :( […] Is it because cbfs_cache comes from a memory pool which can support only 2 allocations? One is consumed by FSP-M Other is consumed by APOB. Only at this point, you are sure that the buffer allocated for FSP-M is freed? -- To view, visit https://review.coreboot.org/c/coreboot/+/58983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51 Gerrit-Change-Number: 58983 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 21:29:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Raul Rangel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Julius Werner. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > > I agree we can look into other solutions, but can we keep it simple for now? […] Ah great, I didn't want to take another detour :) IMO, it needs to be at a lower layer. APOB prefetch (start_apob_cache_read) only uses fmap_locate_area_as_rdev, so making it call into cbfs gets a little strange... Come to think of it, ELOG also uses a raw region. I think we can make threads cheaper. Before, when they used v1 cpu_info(), the stack size needed to match the BSP stack size. Now that it's decoupled we can in theory resize the thread stack size. We could add a simple runtime stack size check that prints out the total stack used when we terminate a thread. This will help tuning that value. -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 21:26:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/thread,soc/amd/common: Delete thread_mutex
by Paul Menzel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner, Rob Barnes, Karthik Ramasubramanian, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59323 ) Change subject: lib/thread,soc/amd/common: Delete thread_mutex ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c6d00a72a37bcc3f9f772c96b61003c280c6b19 Gerrit-Change-Number: 59323 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 20:56:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Julius Werner (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Raul Rangel, Patrick Georgi, Martin Roth, Tim Wawrzynczak. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I agree we can look into other solutions, but can we keep it simple for now? I'm not saying any of this should be done immediately or block this patch, I'm just trying to discuss where we'd like to see this go eventually. That doesn't mean you have to do it. > We would need to devise a way to make the `delegator` boot device get handles to the `platform` boot devices. Oh, I was thinking about attaching at a higher level actually. If you want error handling you can't just use rdev_writeat(), you'd need to replace those calls (in the elog code and wherever) with some new API like rdev_deferred_write(&rdev, buffer, offset, size, DEFERRED_ERROR_IGNORE) which then hooks it into a queue where the thread comes by to pick it up and do the actual rdev_write() at some later point. That would require rewriting all drivers we worry about interfering to use these APIs, of course (and if prefetching is disabled those calls would just decay into direct rdev_writeat() calls). Our threads aren't that cheap (memory-wise), that's why I'd suggest combining this with the prefetch task. Can't write and read at the same time anyway, and whether you step through one or two queues doesn't make much of a difference. -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 20:51:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/*: Enable dGPU temp/fan reporting
by Jeremy Soller (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Tim Crawford. Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59123 ) Change subject: mb/system76/*: Enable dGPU temp/fan reporting ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7 Gerrit-Change-Number: 59123 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 20:44:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/system76/ec: acpi: Add dGPU thermal reporting
by Jeremy Soller (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Tim Crawford. Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57881 ) Change subject: ec/system76/ec: acpi: Add dGPU thermal reporting ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae1063ee6a082a77ed026178eb9471bbc2b2fadf Gerrit-Change-Number: 57881 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 20:44:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021