coreboot-gerrit November 2021

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Karthik Ramasubramanian (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian. Hello build bot (Jenkins), Andrey Pronin, Raul Rangel, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59476 to look at the new patch set (#5). Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... src/security/vboot: Set up secure counter space in TPM NVRAM High Definition (HD) protected content playback requires secure counters that are updated at regular interval while the protected content is playing. To support similar use-cases, define space for secure counters in TPM NVRAM and initialize them. These counters are defined once during the factory initialization stage. Also add VBOOT_DEFINE_WIDEVINE_COUNTERS config item to enable these secure counters only on the mainboard where they are required/used. BUG=b:205261728 TEST=Build and boot to OS in guybrush. Ensure that the secure counters are defined successfully in TPM NVRAM space. tlcl_define_space: response is 0 tlcl_define_space: response is 0 tlcl_define_space: response is 0 tlcl_define_space: response is 0 On reboot if forced to redefine the space, it is identified as already defined. tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/vboot/Kconfig M src/security/vboot/antirollback.h M src/security/vboot/secdata_tpm.c 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59476/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/trogdor: change pin define for quackingstick
by Bob Moragues (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Bob Moragues, Sheng-Liang Pan. Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59533 ) Change subject: mb/google/trogdor: change pin define for quackingstick ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0 Gerrit-Change-Number: 59533 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 23:16:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]mb/google/brya/var/kano: exchange i2c port for touchscreen/cr50
by Tim Wawrzynczak (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: David Wu, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59473 ) Change subject: [WIP]mb/google/brya/var/kano: exchange i2c port for touchscreen/cr50 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/59473/comment/e4bd0f8a_dc16ca28 PS3, Line 79: default 0x1 if BOARD_GOOGLE_KANO > Hi Tim and Nick, […] Ah right.... suppose that means right now we do not have a way to support a single build target having a different TPM bus (can't be selected at runtime right now).... let me look into this. -- To view, visit https://review.coreboot.org/c/coreboot/+/59473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c900568adb119871d6374294a27195d75699ea6 Gerrit-Change-Number: 59473 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 23:13:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/cbfs: Use a work queue for cbfs_preload
by Raul Rangel (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Julius Werner, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58954 ) Change subject: lib/cbfs: Use a work queue for cbfs_preload ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/58954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965385e70793557cb14e4b925ae9afbe66a12c0e Gerrit-Change-Number: 58954 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 23:13:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage
by Karthik Ramasubramanian (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 ) Change subject: soc/amd/cezanne/romstage: Call preload_ramstage ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/cezanne/fsp_m_params.c: https://review.coreboot.org/c/coreboot/+/58983/comment/bf78a11c_35f45d79 PS5, Line 181: preload_ramstage(); > Ah yeah I should have mentioned the mem_pool limitation. […] Makes sense. I see that APOB has its own thread and buffer to cache the data. -- To view, visit https://review.coreboot.org/c/coreboot/+/58983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51 Gerrit-Change-Number: 58983 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 23:13:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: emulation/qemu-i440fx,q35: avoid writing to ROM
by Julian Stecklina (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Nico Huber, Paul Menzel. Julian Stecklina has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59474 ) Change subject: emulation/qemu-i440fx,q35: avoid writing to ROM ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59474/comment/d82bfe60_0dd00de1 PS1, Line 16: Qemu > Nit: QEMU Fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/59474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cefbc31f917021236105f7dc969118d612ac399 Gerrit-Change-Number: 59474 Gerrit-PatchSet: 2 Gerrit-Owner: Julian Stecklina Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Peter Stuge <peter(a)stuge.se> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 22:59:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: emulation/qemu-i440fx,q35: avoid writing to ROM
by Julian Stecklina (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Nico Huber, Julian Stecklina. Hello build bot (Jenkins), Nico Huber, Paul Menzel, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59474 to look at the new patch set (#2). Change subject: emulation/qemu-i440fx,q35: avoid writing to ROM ...................................................................... emulation/qemu-i440fx,q35: avoid writing to ROM libcbfs has a workaround to avoid writing to ROM areas: /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { This workaround is not triggered in QEMU, because BOOT_DEVICE_MEMORY_MAPPED is only selected for SPI boot devices. This results in confusing (to the VMM developer) writes to read-only memory. As far as I can tell, this issue is weird but harmless, because the code does memcpy to ROM with source == destination. The concensus in the mailing list thread [1] was that it's worthwhile to be fixed regardless. [1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/KDI… Change-Id: I5cefbc31f917021236105f7dc969118d612ac399 Signed-off-by: Julian Stecklina <julian.stecklina(a)cyberus-technology.de> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59474/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cefbc31f917021236105f7dc969118d612ac399 Gerrit-Change-Number: 59474 Gerrit-PatchSet: 2 Gerrit-Owner: Julian Stecklina Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Peter Stuge <peter(a)stuge.se> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julian Stecklina Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [Test] mb/google/brya/var/redrix: Fix TCSS port numbering
by Anil Kumar K (Code Review) 22 Nov '21

22 Nov '21

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59553 ) Change subject: [Test] mb/google/brya/var/redrix: Fix TCSS port numbering ...................................................................... [Test] mb/google/brya/var/redrix: Fix TCSS port numbering redrix board has two ports one on MB and another on DB. Use the correct numbering to avoid issues while port access and retimer updates Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I4c1df6d0d454e14f5529236fc27c3538c27def1f --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59553/1 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index ce9ba37..4e9205e 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -152,7 +152,7 @@ device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[0].typec_port device generic 0 on end end end @@ -422,8 +422,8 @@ chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" - device ref tcss_usb3_port3 on end + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/59553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c1df6d0d454e14f5529236fc27c3538c27def1f Gerrit-Change-Number: 59553 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage
by Raul Rangel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 ) Change subject: soc/amd/cezanne/romstage: Call preload_ramstage ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/cezanne/fsp_m_params.c: https://review.coreboot.org/c/coreboot/+/58983/comment/dc194e26_fb1f05fa PS5, Line 181: preload_ramstage(); > Is it because cbfs_cache comes from a memory pool which can support only 2 allocations? […] Ah yeah I should have mentioned the mem_pool limitation. So the APOB doesn't actually require the cbfs_cache, the 2nd allocation comes from allocating the cbfs_preload_context for the FSP-M preload. -- To view, visit https://review.coreboot.org/c/coreboot/+/58983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51 Gerrit-Change-Number: 58983 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Nov 2021 22:47:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Paul Menzel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59476/comment/5a6b883c_d8a44e87 PS4, Line 13: add a config item Please mention the name. > add the config item … File src/security/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/59476/comment/e4d381fc_962b0cec PS4, Line 289: Setup Set up -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 22:37:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021