coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/qualcomm/common/usb: Add support for common USB driver
by Ravi kumar (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56091 to look at the new patch set (#39). Change subject: soc/qualcomm/common/usb: Add support for common USB driver ...................................................................... soc/qualcomm/common/usb: Add support for common USB driver Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 --- M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/trogdor/romstage.c A src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/qusb_phy.h A src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/usb_common.h R src/soc/qualcomm/common/usb/qmpv3_usb_phy.c A src/soc/qualcomm/common/usb/qmpv4_usb_phy.c A src/soc/qualcomm/common/usb/qusb_phy.c A src/soc/qualcomm/common/usb/snps_usb_phy.c A src/soc/qualcomm/common/usb/usb.c M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/include/soc/usb.h 13 files changed, 1,028 insertions(+), 416 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56091/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/56091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Gerrit-Change-Number: 56091 Gerrit-PatchSet: 39 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: timestamp: Add new helper functions
by Bora Guvendik (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Julius Werner, Subrata Banik, Angel Pons, Aaron Durbin. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add new helper functions ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/af258b0d_222f56c5 PS3, Line 7: Add helper fucntions > > I guess we have other options as well to create 2 cbmem tables […] Julius, please see the following 2 patches, I implemented your suggestion (hope understood correctly). https://review.coreboot.org/c/coreboot/+/59554/1 https://review.coreboot.org/c/coreboot/+/59555/2 I think it ended up being more complicated than this rewind api. 0:1st timestamp 0 944:CSE sent 'Boot Stall Done' to PMC 296,000 945:CSE started to handle ICC configuration 303,000 (7,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 308,000 (5,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 1,074,000 (766,000) 11:start of bootblock 1,101,606 (27,606) 12:end of bootblock 1,161,989 (60,382) I had to qsort a second time because below is what it looks like after the initial qsort, the largest negative shows up first. 0:1st timestamp 0 947:CSE received 'CPU Reset Done Ack sent' from PMC 1,074,000 946:CSE sent 'Host BIOS Prep Done' to PMC 308,000 (18,483,711,495,936,957) 945:CSE started to handle ICC configuration 303,000 (18,483,711,496,697,957) 944:CSE sent 'Boot Stall Done' to PMC 296,000 (18,483,711,496,695,957) 11:start of bootblock 1,101,606 (805,606) 12:end of bootblock 1,161,989 (60,382) -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 00:54:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbmem: Rebase to handle negative timestamps
by Bora Guvendik (Code Review) 23 Nov '21

23 Nov '21

Bora Guvendik has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59555 ) Change subject: util/cbmem: Rebase to handle negative timestamps ...................................................................... util/cbmem: Rebase to handle negative timestamps Rebase all of the timestamps to the lowest(negative) value in the list when displaying them. TEST=Boot to OS after adding negative timestamps, cbmem -t timestamp_add(TS_ME_BOOT_STALL_DONE, 0 - ts[6]); timestamp_add(TS_ME_ICC_CONFIG_START, 0 - ts[7]); timestamp_add(TS_ME_HOST_BOOT_PREP_DONE, 0 - ts[10]); timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, 0 - ts[19]); 0:1st timestamp 0 944:CSE sent 'Boot Stall Done' to PMC 296,000 945:CSE started to handle ICC configuration 303,000 (7,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 308,000 (5,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 1,074,000 (766,000) 11:start of bootblock 1,101,606 (27,606) 12:end of bootblock 1,161,989 (60,382) Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I7eb519c360e066d48dde205401e4ccd3b0b3d8a5 --- M util/cbmem/cbmem.c 1 file changed, 49 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/59555/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb519c360e066d48dde205401e4ccd3b0b3d8a5 Gerrit-Change-Number: 59555 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/cbmem: Rebase to handle negative timestamps
by build bot (Jenkins) (Code Review) 23 Nov '21

23 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59555 ) Change subject: util/cbmem: Rebase to handle negative timestamps ...................................................................... Patch Set 1: (3 comments) File util/cbmem/cbmem.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134043): https://review.coreboot.org/c/coreboot/+/59555/comment/00ecfb4b_508024cc PS1, Line 612: tse = &sorted_tst_p->entries[i]; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134043): https://review.coreboot.org/c/coreboot/+/59555/comment/543a69c0_11146245 PS1, Line 612: tse = &sorted_tst_p->entries[i]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134043): https://review.coreboot.org/c/coreboot/+/59555/comment/b6ffd0f5_164889b0 PS1, Line 614: /* Rebase all timestamps. */ code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/59555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb519c360e066d48dde205401e4ccd3b0b3d8a5 Gerrit-Change-Number: 59555 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 00:23:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbmem: Rebase to handle negative timestamps
by Bora Guvendik (Code Review) 23 Nov '21

23 Nov '21

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59555 ) Change subject: util/cbmem: Rebase to handle negative timestamps ...................................................................... util/cbmem: Rebase to handle negative timestamps Rebase all of the timestamps to the lowest(negative) value in the list when displaying them. TEST=Boot to OS after adding negative timestamps, cbmem -t timestamp_add(TS_ME_BOOT_STALL_DONE, 0 - ts[6]); timestamp_add(TS_ME_ICC_CONFIG_START, 0 - ts[7]); timestamp_add(TS_ME_HOST_BOOT_PREP_DONE, 0 - ts[10]); timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, 0 - ts[19]); 0:1st timestamp 0 944:CSE sent 'Boot Stall Done' to PMC 296,000 945:CSE started to handle ICC configuration 303,000 (7,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 308,000 (5,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 1,074,000 (766,000) 11:start of bootblock 1,101,606 (27,606) 12:end of bootblock 1,161,989 (60,382) Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I7eb519c360e066d48dde205401e4ccd3b0b3d8a5 --- M util/cbmem/cbmem.c 1 file changed, 49 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/59555/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 085e004..5aec7fd 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -589,6 +589,39 @@ return 0; } +static void rebase_timestamp_entries(struct timestamp_table *sorted_tst_p, + uint32_t num_entries) +{ + uint64_t rebase_delta; + struct timestamp_entry *tse; + + if (!sorted_tst_p || num_entries <= 0) + return; + + if (sorted_tst_p->entries[0].entry_stamp >= 0) + return; + + rebase_delta = 0 - sorted_tst_p->entries[0].entry_stamp; + + if (rebase_delta > sorted_tst_p->base_time) + sorted_tst_p->base_time = 0; + else + sorted_tst_p->base_time -= rebase_delta; + + for (uint32_t i = 0; i < num_entries; i++) { + tse = &sorted_tst_p->entries[i]; + + /* Rebase all timestamps. */ + if (tse->entry_stamp > 0) + tse->entry_stamp += rebase_delta; + else + tse->entry_stamp = 0 - tse->entry_stamp; + } + + qsort(&sorted_tst_p->entries[0], sorted_tst_p->num_entries, + sizeof(struct timestamp_entry), compare_timestamp_entries); +} + /* dump the timestamp table */ static void dump_timestamps(int mach_readable) { @@ -621,15 +654,6 @@ if (!tst_p) die("Unable to map full timestamp table\n"); - /* Report the base time within the table. */ - prev_stamp = 0; - if (mach_readable) - timestamp_print_parseable_entry(0, tst_p->base_time, - prev_stamp); - else - timestamp_print_entry(0, tst_p->base_time, prev_stamp); - prev_stamp = tst_p->base_time; - sorted_tst_p = malloc(size); if (!sorted_tst_p) die("Failed to allocate memory"); @@ -638,6 +662,22 @@ qsort(&sorted_tst_p->entries[0], sorted_tst_p->num_entries, sizeof(struct timestamp_entry), compare_timestamp_entries); + /* + * If there are negative timestamp entries, rebase all of the + * timestamps to the lowest one in the list. + */ + if (sorted_tst_p->entries[0].entry_stamp < 0) + rebase_timestamp_entries(sorted_tst_p, sorted_tst_p->num_entries); + + /* Report the base time within the table. */ + prev_stamp = 0; + if (mach_readable) + timestamp_print_parseable_entry(0, sorted_tst_p->base_time, + prev_stamp); + else + timestamp_print_entry(0, sorted_tst_p->base_time, prev_stamp); + prev_stamp = sorted_tst_p->base_time; + total_time = 0; for (uint32_t i = 0; i < sorted_tst_p->num_entries; i++) { uint64_t stamp; -- To view, visit https://review.coreboot.org/c/coreboot/+/59555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb519c360e066d48dde205401e4ccd3b0b3d8a5 Gerrit-Change-Number: 59555 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: timestamp: Allow timestamp_add to accept a negative number
by Bora Guvendik (Code Review) 23 Nov '21

23 Nov '21

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59554 ) Change subject: timestamp: Allow timestamp_add to accept a negative number ...................................................................... timestamp: Allow timestamp_add to accept a negative number Change timestamp_add to accept negative values for events that took place before coreboot started executing. TEST=Boot to OS, check cbmem -t Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I90afc13a8e92693d86e3358f05e0a0cb7cdbca9b --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/include/timestamp.h M src/lib/timestamp.c 3 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59554/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 98fe552..913b09a 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -7,7 +7,7 @@ struct timestamp_entry { uint32_t entry_id; - uint64_t entry_stamp; + int64_t entry_stamp; } __packed; struct timestamp_table { diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 647cd13..cbe9934 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -19,7 +19,7 @@ * inside REGION(timestamp) before cbmem comes online. For later stages, timestamps * added before cbmem_[recovery|initialize] calls will be lost. */ -void timestamp_add(enum timestamp_id id, uint64_t ts_time); +void timestamp_add(enum timestamp_id id, int64_t ts_time); /* Calls timestamp_add with current timestamp. */ void timestamp_add_now(enum timestamp_id id); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 7347d07..7bc96c6 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -102,7 +102,7 @@ } static void timestamp_add_table_entry(struct timestamp_table *ts_table, - enum timestamp_id id, uint64_t ts_time) + enum timestamp_id id, int64_t ts_time) { struct timestamp_entry *tse; @@ -117,7 +117,7 @@ printk(BIOS_ERR, "ERROR: Timestamp table full\n"); } -void timestamp_add(enum timestamp_id id, uint64_t ts_time) +void timestamp_add(enum timestamp_id id, int64_t ts_time) { struct timestamp_table *ts_table; @@ -131,7 +131,9 @@ return; } - ts_time -= ts_table->base_time; + if (ts_time >= 0) + ts_time -= ts_table->base_time; + timestamp_add_table_entry(ts_table, id, ts_time); if (CONFIG(TIMESTAMPS_ON_CONSOLE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/59554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90afc13a8e92693d86e3358f05e0a0cb7cdbca9b Gerrit-Change-Number: 59554 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [Test] mb/google/brya/var/redrix: Fix TCSS port numbering
by Anil Kumar K (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak. Hello build bot (Jenkins), Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59553 to look at the new patch set (#4). Change subject: [Test] mb/google/brya/var/redrix: Fix TCSS port numbering ...................................................................... [Test] mb/google/brya/var/redrix: Fix TCSS port numbering redrix board has two ports one on MB and another on DB. Use the correct numbering to avoid issues while port access and retimer updates Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I4c1df6d0d454e14f5529236fc27c3538c27def1f --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59553/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c1df6d0d454e14f5529236fc27c3538c27def1f Gerrit-Change-Number: 59553 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/redrix: Fix TCSS port numbering
by Anil Kumar K (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59553 to look at the new patch set (#3). Change subject: mb/google/brya/var/redrix: Fix TCSS port numbering ...................................................................... mb/google/brya/var/redrix: Fix TCSS port numbering redrix board has two ports one on MB and another on DB. Use the correct numbering to avoid issues while port access and retimer updates Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I4c1df6d0d454e14f5529236fc27c3538c27def1f --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59553/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c1df6d0d454e14f5529236fc27c3538c27def1f Gerrit-Change-Number: 59553 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Karthik Ramasubramanian (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Paul Menzel, Julius Werner, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59476/comment/02e2d7df_8b94b340 PS4, Line 13: add a config item > Please mention the name. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 23:18:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Enable secure counters
by Karthik Ramasubramanian (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59477 to look at the new patch set (#5). Change subject: soc/amd/cezanne: Enable secure counters ...................................................................... soc/amd/cezanne: Enable secure counters Guybrush uses secure counters to protect against High Definition (HD) protected content rollback. These secure counters are hosted in TPM NVRAM. Enable secure counters so that they are defined in PSP verstage. BUG=b:205261728 TEST=Build and boot to OS in Guybrush. Ensure that the secure counters are defined successfully in TPM NVRAM. Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/59477/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca Gerrit-Change-Number: 59477 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021