coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Tim Wawrzynczak (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Raul Rangel, Patrick Georgi, Martin Roth, Julius Werner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > That's what I meant. […] Actually I have both concerns, it seems slightly odd to have a function for each file in … [View More]

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59509 ) Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/Kconfig: https://review.coreboot.org/c/coreboot/+/59509/… [View More]comment/647757fb_c039a37c PS4, Line 7: config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using Thermal PCI device : for chipsets till Ice Lake PCH. : : config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using PMC PWRMBASE : for chipsets since Tiger Lake PCH. > Another way could be […] Meh, looks like Kconfig doesn't like my idea... I'd simply use a preprocessor check inside `thermal.h`: #if CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) && CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC) #error "<insert error message here>" #endif Or, we could define the `GET_LTT_VALUE` macro independently for each case: #if CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) /* Trip Point Temp = (LTT / 2 - 50 degree C) */ #define GET_LTT_VALUE(x) (((x) + 50) * (2)) #endif #if CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC) /* * Trip Point = T2L | T1L | T0L where T2L > T1L > T0L * T2L = Bit 28:20 * T1L = Bit 18:10 * T0L = Bit 8:0 */ #define GET_LTT_VALUE(x) (((x) + 10) << 20 | ((x) + 5) << 10 | (x)) #endif This way, there will be a macro redefinition error if both symbols are enabled. If none of them is enabled, something will be undefined. -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 22 Nov 2021 17:35:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment [View Less]

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Change in coreboot[master]: configs: Add config file for LabTop Mk IV
by Sean Rhodes (Code Review) 22 Nov '21

22 Nov '21

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58429 ) Change subject: configs: Add config file for LabTop Mk IV ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/58429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: … [View More]

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Change in coreboot[master]: mainboard/starlabs: Add LabTop Mk IV
by Sean Rhodes (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Andy Pont, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mainboard/starlabs: Add LabTop Mk IV ...................................................................... Patch Set 65: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings … [View More]

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Change in coreboot[master]: security/intel/txt/ramstage.c: Fix HEAP_ACM element size calculation
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Michał Żygowski. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59519 ) Change subject: security/intel/txt/ramstage.c: Fix HEAP_ACM element size calculation ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59519/comment/2437518d_1c2c1e58 PS3, Line 7: Fix > I have explained that in the comment inside the … [View More]

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Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Michał Żygowski, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59521 ) Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed ...................................................................... Patch Set 3: (1 comment) File src/security/intel/txt/romstage.c: https://review.coreboot.org/c/coreboot/+/59521/comment/cd2ceb77_41595682 PS3, Line 138: wrmsr(… [View More]

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by EricR Lai (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59509 ) Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/Kconfig: https://review.coreboot.org/c/coreboot/+/59509/… [View More]comment/c974b05d_e33c2f65 PS4, Line 7: config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using Thermal PCI device : for chipsets till Ice Lake PCH. : : config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using PMC PWRMBASE : for chipsets since Tiger Lake PCH. > kind like we override the config in the mainboard Kconfig. Another way could be config SOC_INTEL_COMMON_BLOCK_THERMAL_TECH int default 1 means PCH 2 means PMC then use the if condition for SOC_INTEL_COMMON_BLOCK_THERMAL_TECH if SOC_INTEL_COMMON_BLOCK_THERMAL_TECH == 1 select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV endif etc.. -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 16:59:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment [View Less]

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Change in coreboot[master]: cpu/intel/hyperthreading: Add missing header <arch/cpu.h>
by Raul Rangel (Code Review) 22 Nov '21

22 Nov '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59356 ) Change subject: cpu/intel/hyperthreading: Add missing header <arch/cpu.h> ...................................................................... cpu/intel/hyperthreading: Add missing header <arch/cpu.h> This file is using cpuid_result and cpuid(). I also removed the spinlock header since it's not used. This is what was previously providing the cpu.h header. BUG=b:179699789 TEST=none Signed-… [View More]

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Patrick Georgi (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Raul Rangel, Martin Roth, Tim Wawrzynczak, Julius Werner. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > > buffering to RAM and writing it all out when the SPI reads are done should work, no? […] That's what I meant.… [View More]

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Raul Rangel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Julius Werner. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > buffering to RAM and writing it all out when the SPI reads are done should work, no? Maybe I miss understood. Are … [View More]

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coreboot-gerrit November 2021