coreboot-gerrit November 2021

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Change in coreboot[master]: Documentation: Add warning about "private" changes on Gerrit
by Felix Singer (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Patrick Georgi. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59229 ) Change subject: Documentation: Add warning about "private" changes on Gerrit ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c8c6cccfd023bc1d839dc5d9544204c88f89c7e Gerrit-Change-Number: 59229 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 16:09:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Raul Rangel (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Julius Werner. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > How much is going on in ELOG or APOB? Does the prefetch use case require a buffer for writes to flas […] Unfortunately the AMD SPI DMA controller is pretty limited. It can only perform reads. Writes requires using command mode API which can only handle 63 bytes per transaction. With the way it's currently implemented, there is a spi_mutex that the SPI DMA controller will grab when performing a transaction. The SPI RW driver will also grab the SPI mutex for ever 63 byte transaction. https://review.coreboot.org/c/coreboot/+/58926 The contention happens if a SPI DMA transaction gets enqueued while writing to the SPI rom. The write will have to wait for the DMA transaction to finish before being started. After the 63 byte write transaction finishes, it's possible for another SPI DMA transaction to be enqueued. Unfortunately the SPI RW code only locks the bus for every 63 byte transaction, not for the whole write. I thought about changing it but it seemed like a lot of risky work. We could in theory make the ELOG/APOB writes happen in a different thread so that it doesn't matter how long they take. This introduces more complexity though, and honestly I just want to finish working on this so I can move on :) -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 16:05:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/*: Disable IME by CMOS option
by Tim Crawford (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Jeremy Soller. Hello build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57621 to look at the new patch set (#4). Change subject: mb/system76/*: Disable IME by CMOS option ...................................................................... mb/system76/*: Disable IME by CMOS option Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H, and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER. The HECI device must be enabled in devicetree for switching modes to function correctly. Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/addw1/cmos.default M src/mainboard/system76/addw1/cmos.layout M src/mainboard/system76/bonw14/cmos.default M src/mainboard/system76/bonw14/cmos.layout M src/mainboard/system76/cml-u/cmos.default M src/mainboard/system76/cml-u/cmos.layout M src/mainboard/system76/darp7/cmos.default M src/mainboard/system76/darp7/cmos.layout M src/mainboard/system76/galp5/cmos.default M src/mainboard/system76/galp5/cmos.layout M src/mainboard/system76/gaze15/cmos.default M src/mainboard/system76/gaze15/cmos.layout M src/mainboard/system76/gaze16/cmos.default M src/mainboard/system76/gaze16/cmos.layout M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/lemp10/cmos.default M src/mainboard/system76/lemp10/cmos.layout M src/mainboard/system76/lemp9/cmos.default M src/mainboard/system76/lemp9/cmos.layout M src/mainboard/system76/oryp5/cmos.default M src/mainboard/system76/oryp5/cmos.layout M src/mainboard/system76/oryp6/cmos.default M src/mainboard/system76/oryp6/cmos.layout M src/mainboard/system76/oryp8/cmos.default M src/mainboard/system76/oryp8/cmos.layout M src/mainboard/system76/oryp8/devicetree.cb M src/mainboard/system76/whl-u/cmos.default M src/mainboard/system76/whl-u/cmos.layout M src/mainboard/system76/whl-u/devicetree.cb 29 files changed, 85 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/57621/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/57621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Gerrit-Change-Number: 57621 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/system76/*: Disable IME by CMOS option
by Tim Crawford (Code Review) 22 Nov '21

22 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57621 to look at the new patch set (#3). Change subject: mb/system76/*: Disable IME by CMOS option ...................................................................... mb/system76/*: Disable IME by CMOS option Add CMOS option to set IME mode. Default to "Disable" for CML and TGL-H, and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER. The HECI device must be enabled in devicetree for switching modes to function correctly. Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/addw1/cmos.default M src/mainboard/system76/addw1/cmos.layout M src/mainboard/system76/bonw14/cmos.default M src/mainboard/system76/bonw14/cmos.layout M src/mainboard/system76/cml-u/cmos.default M src/mainboard/system76/cml-u/cmos.layout M src/mainboard/system76/darp7/cmos.default M src/mainboard/system76/darp7/cmos.layout M src/mainboard/system76/galp5/cmos.default M src/mainboard/system76/galp5/cmos.layout M src/mainboard/system76/gaze15/cmos.default M src/mainboard/system76/gaze15/cmos.layout M src/mainboard/system76/gaze16/cmos.default M src/mainboard/system76/gaze16/cmos.layout M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/lemp10/cmos.default M src/mainboard/system76/lemp10/cmos.layout M src/mainboard/system76/lemp9/cmos.default M src/mainboard/system76/lemp9/cmos.layout M src/mainboard/system76/oryp5/cmos.default M src/mainboard/system76/oryp5/cmos.layout M src/mainboard/system76/oryp6/cmos.default M src/mainboard/system76/oryp6/cmos.layout M src/mainboard/system76/oryp8/cmos.default M src/mainboard/system76/oryp8/cmos.layout M src/mainboard/system76/oryp8/devicetree.cb M src/mainboard/system76/whl-u/cmos.default M src/mainboard/system76/whl-u/cmos.layout M src/mainboard/system76/whl-u/devicetree.cb 29 files changed, 85 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/57621/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/57621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Gerrit-Change-Number: 57621 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by EricR Lai (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59509 ) Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/Kconfig: https://review.coreboot.org/c/coreboot/+/59509/comment/64b28e1e_4d296bde PS4, Line 7: config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using Thermal PCI device : for chipsets till Ice Lake PCH. : : config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using PMC PWRMBASE : for chipsets since Tiger Lake PCH. > config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV […] kind like we override the config in the mainboard Kconfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 15:17:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by EricR Lai (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59509 ) Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/thermal/Kconfig: https://review.coreboot.org/c/coreboot/+/59509/comment/53d98d95_2b1d0365 PS4, Line 7: config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using Thermal PCI device : for chipsets till Ice Lake PCH. : : config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC : bool : default n : select SOC_INTEL_COMMON_BLOCK_THERMAL : help : This option allows to configure PCH thermal registers using PMC PWRMBASE : for chipsets since Tiger Lake PCH. > @Eric, can you please help me to understand this little better. config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV bool default n select SOC_INTEL_COMMON_BLOCK_THERMAL help This option allows to configure PCH thermal registers using Thermal PCI device for chipsets till Ice Lake PCH. config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC bool default y select SOC_INTEL_COMMON_BLOCK_THERMAL help This option allows to configure PCH thermal registers using PMC PWRMBASE for chipsets since Tiger Lake PCH. if !SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV bool default y select SOC_INTEL_COMMON_BLOCK_THERMAL help This option allows to configure PCH thermal registers using Thermal PCI device for chipsets till Ice Lake PCH. endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 15:16:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Add PLD to EC conn in ACPI table
by Felix Held (Code Review) 22 Nov '21

22 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59401 ) Change subject: ec/google/chromeec: Add PLD to EC conn in ACPI table ...................................................................... ec/google/chromeec: Add PLD to EC conn in ACPI table Given EC CON and associated USB port objects, custom_pld or pld_group information is retrieved from port and added to ACPI table as _PLD field for typec connector. BUG=b:202446737 TEST=emerge-brya coreboot & SSDT dump in Brya test device Signed-off-by: Won Chung <wonchung(a)google.com> Change-Id: Ibc56ecd4e8954ffaace3acd9528a064b5fa2cf6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59401 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpigen_usb.c M src/ec/google/chromeec/ec_acpi.c M src/include/acpi/acpigen_usb.h 3 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index 7448b3b..2868fee 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_device.h> +#include <acpi/acpi_pld.h> #include <acpi/acpigen.h> #include <acpi/acpigen_usb.h> @@ -132,5 +133,8 @@ add_custom_dsd_property(dsd, port_number); acpi_dp_write(dsd); + /* Add PLD */ + acpigen_write_pld(config->pld); + acpigen_pop_len(); /* Device */ } diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 0598364..4fcc679 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_device.h> +#include <acpi/acpi_pld.h> #include <acpi/acpigen.h> #include <acpi/acpigen_ps2_keybd.h> #include <acpi/acpigen_usb.h> @@ -117,6 +118,27 @@ acpi_dp_add_string(dsd, "port-location", port_location_to_str(port_caps.port_location)); } +static void get_pld_from_usb_ports(struct acpi_pld *pld, + struct device *usb2_port, struct device *usb3_port, + struct device *usb4_port) +{ + struct drivers_usb_acpi_config *config = NULL; + + if (usb4_port) + config = usb4_port->chip_info; + else if (usb3_port) + config = usb3_port->chip_info; + else if (usb2_port) + config = usb2_port->chip_info; + + if (config) { + if (config->use_custom_pld) + *pld = config->custom_pld; + else + acpi_pld_fill_usb(pld, config->type, &config->group); + } +} + static void fill_ssdt_typec_device(const struct device *dev) { struct ec_google_chromeec_config *config = dev->chip_info; @@ -126,6 +148,7 @@ struct device *usb2_port; struct device *usb3_port; struct device *usb4_port; + struct acpi_pld pld = {0}; if (google_chromeec_get_num_pd_ports(&num_ports)) return; @@ -146,6 +169,8 @@ usb4_port = NULL; get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port); + get_pld_from_usb_ports(&pld, usb2_port, usb3_port, usb4_port); + struct typec_connector_class_config typec_config = { .power_role = port_caps.power_role_cap, .try_power_role = port_caps.try_power_role_cap, @@ -156,6 +181,7 @@ .orientation_switch = config->mux_conn[i], .usb_role_switch = config->mux_conn[i], .mode_switch = config->mux_conn[i], + .pld = &pld, }; acpigen_write_typec_connector(&typec_config, i, add_port_location); diff --git a/src/include/acpi/acpigen_usb.h b/src/include/acpi/acpigen_usb.h index efc31f3..8042874 100644 --- a/src/include/acpi/acpigen_usb.h +++ b/src/include/acpi/acpigen_usb.h @@ -3,6 +3,8 @@ #ifndef ACPI_ACPIGEN_USB_H #define ACPI_ACPIGEN_USB_H +#include <acpi/acpi_pld.h> + enum usb_typec_power_role { TYPEC_POWER_ROLE_SOURCE, TYPEC_POWER_ROLE_SINK, @@ -39,6 +41,7 @@ * host or device, for the USB port * @mode_switch: Reference to the ACPI device that controls routing of data lines to * various endpoints (xHCI, DP, etc.) on the SoC. + * @pld: Reference to PLD information. */ struct typec_connector_class_config { enum usb_typec_power_role power_role; @@ -50,6 +53,7 @@ const struct device *orientation_switch; const struct device *usb_role_switch; const struct device *mode_switch; + const struct acpi_pld *pld; }; typedef void (*add_custom_dsd_property_cb)(struct acpi_dp *dsd, int port_number); -- To view, visit https://review.coreboot.org/c/coreboot/+/59401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc56ecd4e8954ffaace3acd9528a064b5fa2cf6f Gerrit-Change-Number: 59401 Gerrit-PatchSet: 3 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Prashant Malani <pmalani(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Use dedicated VBT files for ADL-M
by Felix Held (Code Review) 22 Nov '21

22 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58202 ) Change subject: mb/intel/adlrvp: Use dedicated VBT files for ADL-M ...................................................................... mb/intel/adlrvp: Use dedicated VBT files for ADL-M ADL-M has its own set of VBT files to pick during execution, this will avoid any conflict with other ADL variants. VBT files added at chrome-internal:4138272 BUG=None TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58202 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid(a)intel.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/adlrvp/mainboard.c 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Selma Bensaid: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index a113683..904673e 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -75,13 +75,14 @@ switch (sku_id) { case ADL_P_LP5_1: case ADL_P_LP5_2: - case ADL_M_LP5: return "vbt_adlrvp_lp5.bin"; + case ADL_M_LP5: + return "vbt_adlrvp_m_lp5.bin"; case ADL_P_DDR5_1: case ADL_P_DDR5_2: return "vbt_adlrvp_ddr5.bin"; case ADL_M_LP4: - return "vbt_adlrvp_lp4.bin"; + return "vbt_adlrvp_m_lp4.bin"; default: return "vbt.bin"; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f Gerrit-Change-Number: 58202 Gerrit-PatchSet: 4 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/ppc64/include/arch/io.h: implement IO functions
by Felix Held (Code Review) 22 Nov '21

22 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57075 ) Change subject: arch/ppc64/include/arch/io.h: implement IO functions ...................................................................... arch/ppc64/include/arch/io.h: implement IO functions Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> arch/ppc64/include/arch/io.h: use proper instructions for IO operations Those instrunctions are: * Load {byte,half,word} and Zero Caching Inhibited indeXed (l*zcix) * Store {byte,half,word} Caching Inhibited indeXed (st*cix) for in* and out*, respectively. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> arch/ppc64/include/arch/io.h: implement istep reporting Change-Id: Ib65c99888ba2e616893a55dff47d2b445052fa7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57075 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/ppc64/include/arch/io.h 1 file changed, 35 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index f8c1121..132a5ce 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -5,31 +5,63 @@ #include <stdint.h> +/* Set MSB to 1 to ignore HRMOR */ +#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000 +#define LPCHC_IO_SPACE 0xD0010000 +#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE) + +/* Enforce In-order Execution of I/O */ +static inline void eieio(void) +{ + asm volatile("eieio" ::: "memory"); +} + static inline void outb(uint8_t value, uint16_t port) { + asm volatile("stbcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); } static inline void outw(uint16_t value, uint16_t port) { + asm volatile("sthcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); } static inline void outl(uint32_t value, uint16_t port) { + asm volatile("stwcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); } static inline uint8_t inb(uint16_t port) { - return 0; + uint8_t buffer; + asm volatile("lbzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); + return buffer; } static inline uint16_t inw(uint16_t port) { - return 0; + uint16_t buffer; + asm volatile("lhzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); + return buffer; } static inline uint32_t inl(uint16_t port) { - return 0; + uint32_t buffer; + asm volatile("lwzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); + return buffer; +} + +static inline void report_istep(uint8_t step, uint8_t substep) +{ + outb(step, 0x81); + outb(substep, 0x82); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/57075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib65c99888ba2e616893a55dff47d2b445052fa7c Gerrit-Change-Number: 57075 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/uart: Let DRIVERS_UART_8250IO also depend on PPC64
by Felix Held (Code Review) 22 Nov '21

22 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57074 ) Change subject: drivers/uart: Let DRIVERS_UART_8250IO also depend on PPC64 ...................................................................... drivers/uart: Let DRIVERS_UART_8250IO also depend on PPC64 There seems to be no operational differences between x86 and PPC64 for UART 8250. Port number is the same. References: * https://github.com/open-power/docs/issues/25 * https://github.com/3mdeb/openpower-coreboot-docs/blob/main/devnotes/porting… Tested on Talos II (https://raptorcs.com/TALOSII/). Works in QEMU as well (actually in QEMU it works even without this change somehow). Change-Id: Ib06001076b8eaa577a8d2159afea20afb610687d Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57074 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/uart/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 41b870f..beba401 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -5,7 +5,7 @@ # FIXME: Shouldn't have a prompt, should default to n, and # should be selected by boards that have it instead. bool "Serial port on SuperIO" - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_PPC64 default n if DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL default n if NO_UART_ON_SUPERIO default y -- To view, visit https://review.coreboot.org/c/coreboot/+/57074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib06001076b8eaa577a8d2159afea20afb610687d Gerrit-Change-Number: 57074 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021