coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
by Michał Żygowski (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59523 ) Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT ...................................................................... Patch Set 3: (1 comment) File src/northbridge/intel/sandybridge/romstage.c: https://review.coreboot.org/c/coreboot/+/59523/comment/b42507d8_bcff0dbd PS2, Line 78: #if CONFIG(INTEL_TXT) > I'm afraid I don't follow. The only redundant MSR writing I see is the one CB:59521 adds. That MSR needs to be written even if TXT is not supported. Okay, just yesterday I was still convinced it shouldn't be written if CPU or chipset is not TXT capable, due to #GP it may cause (according to TXT BIOS spec). -- To view, visit https://review.coreboot.org/c/coreboot/+/59523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Gerrit-Change-Number: 59523 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 16:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/tpm: Add firmware-power-managed DSD property
by Karthik Ramasubramanian (Code Review) 22 Nov '21

22 Nov '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59479 ) Change subject: drivers/tpm: Add firmware-power-managed DSD property ...................................................................... drivers/tpm: Add firmware-power-managed DSD property Introduce firmware-power-managed DSD ACPI property for TPM devices. This property can be checked by the kernel TPM driver to override how the TPM power states are managed. This is a tri-state flag, true, false, or unset. So an enum used to keep the flag is unset by default. When firmware-power-managed is true, the kernel driver will not send a shutdown during s2idle/s0i3 suspend. BUG=b:200578885 BRANCH=None TEST=TPM shutdown is triggered on s0ix suspend on guybrush with patched kernel Change-Id: Ia48ead856fc0c6e637a2e07a5ecc58423f599c5b Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59479 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/drivers/i2c/tpm/chip.c M src/drivers/i2c/tpm/chip.h 2 files changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index 07791c3..3a2f8aa 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -11,6 +11,7 @@ static void i2c_tpm_fill_ssdt(const struct device *dev) { + struct acpi_dp *dsd; struct drivers_i2c_tpm_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); struct acpi_i2c i2c = { @@ -47,6 +48,21 @@ acpigen_write_resourcetemplate_footer(); + /* _DSD, Device-Specific Data */ + dsd = acpi_dp_new_table("_DSD"); + switch (config->power_managed_mode) { + case TPM_FIRMWARE_POWER_MANAGED: + acpi_dp_add_integer(dsd, "firmware-power-managed", 1); + break; + case TPM_KERNEL_POWER_MANAGED: + acpi_dp_add_integer(dsd, "firmware-power-managed", 0); + break; + case TPM_DEFAULT_POWER_MANAGED: + default: + /* Leave firmware-power-managed unset */ + } + acpi_dp_write(dsd); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ diff --git a/src/drivers/i2c/tpm/chip.h b/src/drivers/i2c/tpm/chip.h index 0ab10d7..4eac7e1 100644 --- a/src/drivers/i2c/tpm/chip.h +++ b/src/drivers/i2c/tpm/chip.h @@ -3,6 +3,12 @@ #include <acpi/acpi_device.h> #include <device/i2c_simple.h> +enum tpm_power_managed_mode { + TPM_DEFAULT_POWER_MANAGED = 0, + TPM_FIRMWARE_POWER_MANAGED, + TPM_KERNEL_POWER_MANAGED, +}; + struct drivers_i2c_tpm_config { const char *hid; /* ACPI _HID (required) */ const char *desc; /* Device Description */ @@ -10,4 +16,5 @@ enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */ struct acpi_irq irq; /* Interrupt */ struct acpi_gpio irq_gpio; /* GPIO interrupt */ + enum tpm_power_managed_mode power_managed_mode; /* TPM power managed mode */ }; 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia48ead856fc0c6e637a2e07a5ecc58423f599c5b Gerrit-Change-Number: 59479 Gerrit-PatchSet: 8 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Patrick Georgi (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Lance Zhao, Raul Rangel, Martin Roth, Tim Wawrzynczak, Julius Werner. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Unfortunately the AMD SPI DMA controller is pretty limited. It can only perform reads So no background writing (without adding a thread, which isn't what we've signed up for when we started coreboot ;-) ) Still: buffering to RAM and writing it all out when the SPI reads are done should work, no? -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 16:30:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/psp_verstage: Init TPM on S0i3 resume
by Karthik Ramasubramanian (Code Review) 22 Nov '21

22 Nov '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58870 ) Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... soc/amd/psp_verstage: Init TPM on S0i3 resume Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. FSDL is handling restoring everything else, so only the minimum TPM initialization is done. Move aoac and i2c init before psp_verstrage_s0i3_resume becasue i2c needs to be ready before attempting to restore tpm. BUG=b:200578885,b:197965075 TEST=Multiple cycles of S0i3 suspend resume. ~66ms of additional delay. BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58870 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/psp_verstage/Kconfig M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 3 files changed, 62 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index 834abaa..6cac8b7 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -5,3 +5,12 @@ Configure PSP Verstage to use Crypto Co-processor (CCP) DMA while accessing the boot device. Select it on platforms which supports using CCP DMA to access the boot device. + +config PSP_INIT_TPM_ON_S0I3_RESUME + bool + depends on TPM2 && VBOOT_STARTS_BEFORE_BOOTBLOCK + default VBOOT_STARTS_BEFORE_BOOTBLOCK + help + If the TPM is reset while in S0i3, it must be reinitialized + during s0i3 resume. This must be performed in PSP verstage since + coreboot is otherwise not involved with s0i3 resume. diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index ef8a9da..606b6a6 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -20,6 +20,7 @@ #define POSTCODE_EARLY_INIT 0x02 #define POSTCODE_LATE_INIT 0x03 #define POSTCODE_VERSTAGE_MAIN 0x04 +#define POSTCODE_VERSTAGE_S0I3_RESUME 0x05 #define POSTCODE_SAVE_BUFFERS 0x0E #define POSTCODE_UPDATE_BOOT_REGION 0x0F @@ -36,6 +37,8 @@ #define POSTCODE_AMD_FW_MISSING 0xC9 #define POSTCODE_CMOS_RECOVERY 0xCA #define POSTCODE_EARLY_INIT_ERROR 0xCB +#define POSTCODE_INIT_TPM_FAILED 0xCC + #define POSTCODE_UNMAP_SPI_ROM 0xF0 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1 diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 71f07c0..2e3d09d 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -12,6 +12,8 @@ #include <pc80/mc146818rtc.h> #include <soc/iomap.h> #include <soc/psp_transfer.h> +#include <security/tpm/tspi.h> +#include <security/tpm/tss.h> #include <security/vboot/vbnv.h> #include <security/vboot/misc.h> #include <security/vboot/symbols.h> @@ -206,11 +208,42 @@ return 0; } +/* + * S0i3 resume in PSP verstage is a special case. The FSDL is restoring mostly + * everything, so do the minimum necessary here. Unlike normal boot, subsequent + * coreboot stages are not run after s0i3 verstage. + * If the TPM is reset in S0i3, it must be re-initialized here. + */ +static void psp_verstage_s0i3_resume(void) +{ + uint32_t rv; + + post_code(POSTCODE_VERSTAGE_S0I3_RESUME); + + printk(BIOS_DEBUG, "Entering PSP verstage S0i3 resume\n"); + + if (!CONFIG(PSP_INIT_TPM_ON_S0I3_RESUME)) + return; + + rv = tpm_setup(true); + if (rv != TPM_SUCCESS) { + printk(BIOS_ERR, "tpm_setup failed rv:%d\n", rv); + reboot_into_recovery(vboot_get_context(), POSTCODE_INIT_TPM_FAILED); + } + + rv = tlcl_disable_platform_hierarchy(); + if (rv != TPM_SUCCESS) { + printk(BIOS_ERR, "tlcl_disable_platform_hierarchy failed rv:%d\n", rv); + reboot_into_recovery(vboot_get_context(), POSTCODE_INIT_TPM_FAILED); + } +} + void Main(void) { uint32_t retval; struct vb2_context *ctx = NULL; void *boot_dev_base; + uint32_t bootmode; /* * Do not use printk() before console_init() @@ -247,18 +280,29 @@ /* mainboard_tpm_init may check board_id, so make sure espi is ready first */ verstage_mainboard_tpm_init(); - printk(BIOS_DEBUG, "calling verstage_mainboard_early_init\n"); - verstage_mainboard_early_init(); - - svc_write_postcode(POSTCODE_LATE_INIT); - fch_io_enable_legacy_io(); - printk(BIOS_DEBUG, "calling verstage_soc_aoac_init\n"); verstage_soc_aoac_init(); printk(BIOS_DEBUG, "calling verstage_soc_i2c_init\n"); verstage_soc_i2c_init(); + /* + * S0i3 resume in PSP verstage is a special case, handle it separately. + * Make sure TPM i2c is ready first. + */ + svc_get_boot_mode(&bootmode); + if (bootmode == PSP_BOOT_MODE_S0i3_RESUME) { + psp_verstage_s0i3_resume(); + unmap_fch_devices(); + svc_exit(0); + } + + printk(BIOS_DEBUG, "calling verstage_mainboard_early_init\n"); + verstage_mainboard_early_init(); + + svc_write_postcode(POSTCODE_LATE_INIT); + fch_io_enable_legacy_io(); + printk(BIOS_DEBUG, "calling verstage_soc_spi_init\n"); verstage_soc_spi_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 19 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Add warning about "private" changes on Gerrit
by Patrick Georgi (Code Review) 22 Nov '21

22 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59229 ) Change subject: Documentation: Add warning about "private" changes on Gerrit ...................................................................... Documentation: Add warning about "private" changes on Gerrit Private changes on Gerrit are a tricky beast in that they're well hidden in the UI and a few other places but still reachable under certain circumstances. Change-Id: I1c8c6cccfd023bc1d839dc5d9544204c88f89c7e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59229 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/getting_started/gerrit_guidelines.md M Documentation/tutorial/part2.md 2 files changed, 7 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 8c91615..68b5cc4 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -193,8 +193,10 @@ * When pushing patches that are not for submission, these should be marked as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as private changes, so that only explicitly added reviewers will see them. These -sorts of patches are frequently posted as ideas or RFCs for the community -to look at. To push a private change, use the command: +sorts of patches are frequently posted as ideas or RFCs for the community to +look at. Note that private changes can still be fetched from Gerrit by anybody +who knows their commit ID, so don't use this for sensitive changes. To push +a private change, use the command: git push origin HEAD:refs/for/master%private * Multiple push options can be combined: diff --git a/Documentation/tutorial/part2.md b/Documentation/tutorial/part2.md index 4ac8574..964057e 100644 --- a/Documentation/tutorial/part2.md +++ b/Documentation/tutorial/part2.md @@ -173,7 +173,9 @@ coreboot.org. **Note:** To submit as a private patch, use `git push origin HEAD:refs/for/master%private`. Submitting as a private patch means that your commit will be on review.coreboot.org, but is only visible to -yourself and those you add as reviewers. +yourself and those you add as reviewers. This mode isn't perfect: Somebody who +knows the commit ID can still fetch the change and everything it refers (e.g. +parent commits). This has been a quick primer on how to submit a change to Gerrit for review using git. You may wish to review the [Gerrit code review workflow -- To view, visit https://review.coreboot.org/c/coreboot/+/59229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c8c6cccfd023bc1d839dc5d9544204c88f89c7e Gerrit-Change-Number: 59229 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Michał Żygowski, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59523 ) Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT ...................................................................... Patch Set 3: (1 comment) File src/northbridge/intel/sandybridge/romstage.c: https://review.coreboot.org/c/coreboot/+/59523/comment/e2856bff_05093747 PS2, Line 78: #if CONFIG(INTEL_TXT) > What about compiling the TXT romstage part always? There's no need to do so. Please use a regular C check and let the compiler optimize out the unreachable code, like I did on Haswell: https://review.coreboot.org/c/coreboot/+/46608/7/src/northbridge/intel/hasw… > Then we could get rid of redundant MSR writing. I'm afraid I don't follow. The only redundant MSR writing I see is the one CB:59521 adds. That MSR needs to be written even if TXT is not supported. -- To view, visit https://review.coreboot.org/c/coreboot/+/59523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Gerrit-Change-Number: 59523 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 16:27:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Rename "internal audio" setting
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58904 ) Change subject: mb/prodrive/hermes: Rename "internal audio" setting ...................................................................... mb/prodrive/hermes: Rename "internal audio" setting The "internal audio connection" setting is actually about the front panel audio. Rename functions and variables to reflect this. Change-Id: I1be8f68ac3e8b91bc4983dc06daa37afb7bdf926 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58904 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Justin van Son <justin.van.son(a)prodrive-technologies.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h M src/mainboard/prodrive/hermes/variants/r04/hda_verb.c 3 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Justin van Son: Looks good to me, but someone else must approve diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index a9c8408..6ae6b89 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -138,7 +138,7 @@ return; /* Enable internal speaker amplifier */ - if (board_cfg->internal_audio_connection == 2) + if (board_cfg->front_panel_audio == 2) mb_hda_amp_enable(1); else mb_hda_amp_enable(0); diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index 9ec4604..0d4e9d8 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -47,7 +47,7 @@ uint8_t usb_powered_in_s5; uint8_t power_state_after_g3; uint8_t blue_rear_vref; - uint8_t internal_audio_connection; + uint8_t front_panel_audio; uint8_t pxe_boot_capability; }; uint8_t raw_settings[9]; diff --git a/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c b/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c index f9a3cb3..b4a3370 100644 --- a/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c +++ b/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c @@ -30,9 +30,9 @@ } } -static u32 get_internal_audio_cfg(uint8_t internal_audio_connection) +static u32 get_front_panel_cfg(uint8_t front_panel_audio) { - switch (internal_audio_connection) { + switch (front_panel_audio) { default: case 0: return AZALIA_PIN_CFG_NC(0); @@ -62,10 +62,10 @@ if (!board_cfg) return; - const u32 config = get_internal_audio_cfg(board_cfg->internal_audio_connection); + const u32 front_panel_cfg = get_front_panel_cfg(board_cfg->front_panel_audio); const u32 verbs[] = { - AZALIA_PIN_CFG(0, 0x1b, config), + AZALIA_PIN_CFG(0, 0x1b, front_panel_cfg), 0x0205000d, /* Pin 37 vrefo hidden register - used as port C vref */ get_port_c_vref_cfg(board_cfg->blue_rear_vref), }; 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1be8f68ac3e8b91bc4983dc06daa37afb7bdf926 Gerrit-Change-Number: 58904 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
by Michał Żygowski (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59521 ) Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed ...................................................................... Patch Set 3: (1 comment) File src/security/intel/txt/romstage.c: https://review.coreboot.org/c/coreboot/+/59521/comment/cdb48166_3b2db152 PS3, Line 138: wrmsr(TXT_UNLOCK_MEMORY_MSR, msr); > I simply don't understand why this is needed. […] I wasn't aware of the existence of the code under src/northbridge/intel/sandybridge/raminit.c I just got the info from Patrick Rudolph in another patch today or yesterday. I may remove it here and just hope evey other uarch does it in FSP/MRC -- To view, visit https://review.coreboot.org/c/coreboot/+/59521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd29d163a2310f0b574fc72d575f23088ab1d11d Gerrit-Change-Number: 59521 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 16:17:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Michał Żygowski, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59521 ) Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed ...................................................................... Patch Set 3: (1 comment) File src/security/intel/txt/romstage.c: https://review.coreboot.org/c/coreboot/+/59521/comment/7466bad9_c475c0e5 PS3, Line 138: wrmsr(TXT_UNLOCK_MEMORY_MSR, msr); > Yes it does, we have a separate discussion in this patch. […] I simply don't understand why this is needed. The write in sandybridge native raminit code is unconditionally executed. In which scenario is the native raminit write skipped? I'm pretty sure MRC.bin also does the write. -- To view, visit https://review.coreboot.org/c/coreboot/+/59521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd29d163a2310f0b574fc72d575f23088ab1d11d Gerrit-Change-Number: 59521 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 16:14:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
by Angel Pons (Code Review) 22 Nov '21

22 Nov '21

Attention is currently required from: Evgeny Zinoviev, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59527 ) Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads ...................................................................... Patch Set 4: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59527/comment/6485b867_ae61776c PS2, Line 7: Sandy Bridge > I know. I even did it on T420, a long time ago. […] Ack https://review.coreboot.org/c/coreboot/+/59527/comment/7c86859c_2016cd80 PS2, Line 12: 0793afe9 > commit 0793afe9 (mb/lenovo/x220: disable ME) Paul beat me to it -- To view, visit https://review.coreboot.org/c/coreboot/+/59527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Gerrit-Change-Number: 59527 Gerrit-PatchSet: 4 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 22 Nov 2021 16:10:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: comment

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coreboot-gerrit November 2021