coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: mb/google/brya/var/kano: Update thermal table
by David Wu (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59572 to look at the new patch set (#2). Change subject: mb/google/brya/var/kano: Update thermal table ...................................................................... mb/google/brya/var/kano: Update thermal table Update thermal setting from thermal team. BUG=b:205648035 TEST=build and verified by thermal team. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: If5082462b79c88ecf510f7a552381c792604366e --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 27 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/59572/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5082462b79c88ecf510f7a552381c792604366e Gerrit-Change-Number: 59572 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/var/kano: Update thermal table.
by David Wu (Code Review) 23 Nov '21

23 Nov '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59572 ) Change subject: mb/google/brya/var/kano: Update thermal table. ...................................................................... mb/google/brya/var/kano: Update thermal table. Update thermal setting from thermal team. BUG=b:205648035 TEST=build and verified by thermal team. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: If5082462b79c88ecf510f7a552381c792604366e --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 27 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/59572/1 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index d7ae3da..56dfc6f 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -59,23 +59,39 @@ .target = DPTF_CPU, .thresholds = { TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), + TEMP_PCT(75, 80), + TEMP_PCT(68, 70), + TEMP_PCT(62, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(40, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(60, 90), + TEMP_PCT(55, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40), + TEMP_PCT(36, 30), } } }" ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), - [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), @@ -83,15 +99,15 @@ register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, - .max_power = 15000, + .min_power = 18000, + .max_power = 28000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { - .min_power = 55000, - .max_power = 55000, + .min_power = 40000, + .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, -- To view, visit https://review.coreboot.org/c/coreboot/+/59572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5082462b79c88ecf510f7a552381c792604366e Gerrit-Change-Number: 59572 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Update SA & IGD DIDs Table Update SA table as ...
by Praveen HP (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: akino.liao(a)intel.com, Rick Lee, Lean Sheng Tan, Patrick Rudolph. Praveen HP has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59559 ) Change subject: soc/intel/elkhartlake: Update SA & IGD DIDs Table Update SA table as per latest EDS (Doc no: 601458). Add extra SKUs accordingly. ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706 Gerrit-Change-Number: 59559 Gerrit-PatchSet: 1 Gerrit-Owner: Rick Lee <rick.lee(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Praveen HP <praveen.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: akino.liao(a)intel.com Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: akino.liao(a)intel.com Gerrit-Attention: Rick Lee <rick.lee(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 09:09:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/primus: Update thermal table for primus
by Ariel Fang (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Tim Wawrzynczak, Sumeet R Pawnikar. Ariel Fang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59182 ) Change subject: mb/google/brya/var/primus: Update thermal table for primus ...................................................................... Patch Set 8: (2 comments) File src/mainboard/google/brya/variants/primus/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59182/comment/9766e972_14464abf PS7, Line 76: ## Disable Active Policy from baseboard : register "policies.active" = "{[0] = {.target=DPTF_NONE}}" > There is no policy defined in the baseboard, so this change might not be required. […] done https://review.coreboot.org/c/coreboot/+/59182/comment/6c9aa7e8_641aa209 PS7, Line 82: CHARGER > This is mapped to which sensor, as per available lists at line 71 to 74 sensors. I modify the TSR options and add the Charger define. -- To view, visit https://review.coreboot.org/c/coreboot/+/59182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d Gerrit-Change-Number: 59182 Gerrit-PatchSet: 8 Gerrit-Owner: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Tue, 23 Nov 2021 08:59:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/corsola: Add an option for SD card initialization
by Rex-BC Chen (Code Review) 23 Nov '21

23 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59571 ) Change subject: mb/google/corsola: Add an option for SD card initialization ...................................................................... mb/google/corsola: Add an option for SD card initialization There is no support for SD card on Corsola reference board, so we add a configuration to disable SD card initialization to prevent setting GPIOs in a mistaken way. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/mainboard.c 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/59571/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index cb6c968..b57e23b 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -30,4 +30,8 @@ config BOOT_DEVICE_SPI_FLASH_BUS int default 7 + +config SDCARD_INIT + bool + default n endif diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index 2ea81e8..d3d55a2 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -9,7 +9,12 @@ static void mainboard_init(struct device *dev) { mtk_msdc_configure_emmc(true); - mtk_msdc_configure_sdcard(); + + if (CONFIG(SDCARD_INIT)) { + printk(BIOS_INFO, "SD card init\n"); + mtk_msdc_configure_sdcard(); + } + setup_usb_host(); if (spm_init()) -- To view, visit https://review.coreboot.org/c/coreboot/+/59571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc Gerrit-Change-Number: 59571 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/corsola: Get RAM code from ADC
by Rex-BC Chen (Code Review) 23 Nov '21

23 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59570 ) Change subject: mb/google/corsola: Get RAM code from ADC ...................................................................... mb/google/corsola: Get RAM code from ADC On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Corsola the RAM code can be read from ADC channel 2 and 3. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513 --- M src/mainboard/google/corsola/Makefile.inc A src/mainboard/google/corsola/boardid.c 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/59570/1 diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index 7995f8a..1a9a1c28 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -7,11 +7,13 @@ verstage-y += reset.c romstage-y += memlayout.ld +romstage-y += boardid.c romstage-y += chromeos.c romstage-y += regulator.c romstage-y += romstage.c ramstage-y += memlayout.ld +ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += regulator.c diff --git a/src/mainboard/google/corsola/boardid.c b/src/mainboard/google/corsola/boardid.c new file mode 100644 index 0000000..285b065 --- /dev/null +++ b/src/mainboard/google/corsola/boardid.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <boardid.h> +#include <console/console.h> +#include <soc/auxadc.h> + +/* board_id is provided by ec/google/chromeec/ec_boardid.c */ + +#define ADC_LEVELS 12 + +enum { + /* RAM IDs */ + RAM_ID_LOW_CHANNEL = 2, + RAM_ID_HIGH_CHANNEL = 3, +}; + +static const unsigned int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + [0] = 74300, + [1] = 211700, + [2] = 318800, + [3] = 428600, + [4] = 541700, + [5] = 665800, + [6] = 781400, + [7] = 900000, + [8] = 1023100, + [9] = 1137000, + [10] = 1240000, + [11] = 1342600, +}; + +static const unsigned int *adc_voltages[] = { + [RAM_ID_LOW_CHANNEL] = ram_voltages, + [RAM_ID_HIGH_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + unsigned int value = auxadc_get_voltage_uv(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const unsigned int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + + printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id); + return id; +} + +uint32_t ram_code(void) +{ + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) { + cached_ram_code = (get_adc_index(RAM_ID_HIGH_CHANNEL) << 4 | + get_adc_index(RAM_ID_LOW_CHANNEL)); + printk(BIOS_DEBUG, "RAM Code: %#02x\n", cached_ram_code); + } + + return cached_ram_code; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513 Gerrit-Change-Number: 59570 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/corsola: Raise little CPU frequency
by Rex-BC Chen (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59569 ) Change subject: mb/google/corsola: Raise little CPU frequency ...................................................................... mb/google/corsola: Raise little CPU frequency Raise little CPU to 2GHz at romstage. TEST=check little core cpu frequency is 2GHz BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d --- M src/mainboard/google/corsola/romstage.c M src/soc/mediatek/mt8186/Makefile.inc 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/59569/1 diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c index d1e9e20..aff496b 100644 --- a/src/mainboard/google/corsola/romstage.c +++ b/src/mainboard/google/corsola/romstage.c @@ -1,11 +1,29 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <console/console.h> +#include <delay.h> #include <soc/mt6366.h> +#include <soc/pll_common.h> +#include <soc/regulator.h> #include <soc/rtc.h> +static void raise_little_cpu_freq(void) +{ + mainboard_set_regulator_vol(MTK_REGULATOR_VPROC12, 1031250); + mainboard_set_regulator_vol(MTK_REGULATOR_VSRAM_PROC12, 1118750); + udelay(200); + mt_pll_raise_little_cpu_freq(2000 * MHz); + mt_pll_raise_cci_freq(1385 * MHz); + + printk(BIOS_INFO, "Check CPU freq: %u KHz, cci: %u KHz\n", + mt_fmeter_get_freq_khz(FMETER_ABIST, 9), + mt_fmeter_get_freq_khz(FMETER_ABIST, 7)); +} + void platform_romstage_main(void) { mt6366_init(); + raise_little_cpu_freq(); rtc_boot(); } diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index b1624a3..fbde650 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c -- To view, visit https://review.coreboot.org/c/coreboot/+/59569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d Gerrit-Change-Number: 59569 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interface
by Rex-BC Chen (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59568 ) Change subject: mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interface ...................................................................... mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interface Add VPROC12/VSRAM_PROC12 to adjust power for raising little CPU frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I59b4627220022a51a116716036a8ba0048039508 --- M src/mainboard/google/corsola/regulator.c M src/soc/mediatek/common/include/soc/regulator.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/59568/1 diff --git a/src/mainboard/google/corsola/regulator.c b/src/mainboard/google/corsola/regulator.c index b1310af..1dd26d3 100644 --- a/src/mainboard/google/corsola/regulator.c +++ b/src/mainboard/google/corsola/regulator.c @@ -18,6 +18,8 @@ [MTK_REGULATOR_VDRAM1] = MT6366_VDRAM1, [MTK_REGULATOR_VMCH] = MT6366_VMCH, [MTK_REGULATOR_VMC] = MT6366_VMC, + [MTK_REGULATOR_VPROC12] = MT6366_VPROC12, + [MTK_REGULATOR_VSRAM_PROC12] = MT6366_VSRAM_PROC12, }; _Static_assert(ARRAY_SIZE(regulator_id) == MTK_REGULATOR_NUM, "regulator_id size error"); diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h index a53d01c..5068f50 100644 --- a/src/soc/mediatek/common/include/soc/regulator.h +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -16,6 +16,8 @@ MTK_REGULATOR_VDRAM1, MTK_REGULATOR_VMCH, MTK_REGULATOR_VMC, + MTK_REGULATOR_VPROC12, + MTK_REGULATOR_VSRAM_PROC12, MTK_REGULATOR_NUM, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59b4627220022a51a116716036a8ba0048039508 Gerrit-Change-Number: 59568 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek/mt8186: fix variable type
by Rex-BC Chen (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59567 ) Change subject: soc/mediatek/mt8186: fix variable type ...................................................................... soc/mediatek/mt8186: fix variable type The types of pwrap_read_field()'s return value and pwrap_write_field()'s `val` argument are u16, so correct the usage in MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ie05ab65ecd9b8ea1379ef74393285c4f5d2db8a4 --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59567/1 diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 406c524..450b783 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -473,7 +473,7 @@ static u32 pmic_get_vcore_vol(void) { - u32 vol_reg; + u16 vol_reg; vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0); return 500000 + vol_reg * 6250; @@ -481,7 +481,7 @@ static void pmic_set_vcore_vol(u32 vcore_uv) { - u32 vol_reg; + u16 vol_reg; assert(vcore_uv >= 500000); assert(vcore_uv <= 1100000); @@ -539,7 +539,7 @@ static u32 pmic_get_vdram1_vol(void) { - u32 vol_reg; + u16 vol_reg; vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); return 500000 + vol_reg * 12500; @@ -547,7 +547,7 @@ static void pmic_set_vdram1_vol(u32 vdram_uv) { - u32 vol_reg; + u16 vol_reg; assert(vdram_uv >= 500000); assert(vdram_uv <= 1300000); @@ -562,7 +562,7 @@ static u32 pmic_get_vddq_vol(void) { int efuse_votrim; - u32 cali_trim; + u16 cali_trim; if (!pwrap_read_field(PMIC_VDDQ_OP_EN, 0x1, 15)) return 0; @@ -575,7 +575,8 @@ static void pmic_set_vddq_vol(u32 vddq_uv) { - int target_mv, dram2_ori_mv, cali_offset_uv, cali_trim; + int target_mv, dram2_ori_mv, cali_offset_uv; + u16 cali_trim; assert(vddq_uv >= 530000); assert(vddq_uv <= 680000); @@ -606,7 +607,8 @@ static u32 pmic_get_vmch_vol(void) { - u32 vol_reg, ret; + u32 ret; + u16 vol_reg; vol_reg = pwrap_read_field(PMIC_VMCH_ANA_CON0, 0x7, 8); @@ -630,7 +632,7 @@ static void pmic_set_vmch_vol(u32 vmch_uv) { - u32 val = 0; + u16 val = 0; switch (vmch_uv) { case 2900000: @@ -656,7 +658,8 @@ static u32 pmic_get_vmc_vol(void) { - u32 vol_reg, ret; + u32 ret; + u16 vol_reg; vol_reg = pwrap_read_field(PMIC_VMC_ANA_CON0, 0xF, 8); @@ -683,7 +686,7 @@ static void pmic_set_vmc_vol(u32 vmc_uv) { - u32 val = 0; + u16 val = 0; switch (vmc_uv) { case 1800000: -- To view, visit https://review.coreboot.org/c/coreboot/+/59567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05ab65ecd9b8ea1379ef74393285c4f5d2db8a4 Gerrit-Change-Number: 59567 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12
by Rex-BC Chen (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59566 ) Change subject: soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12 ...................................................................... soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12 To raise little CPU frequency, add support for VPROC12 and VSRAM_PROC12 of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo(a)mediatek.corp-partner.google.com> Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904 --- M src/soc/mediatek/mt8186/include/soc/mt6366.h M src/soc/mediatek/mt8186/mt6366.c 2 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59566/1 diff --git a/src/soc/mediatek/mt8186/include/soc/mt6366.h b/src/soc/mediatek/mt8186/include/soc/mt6366.h index 76fcf54..af77da2 100644 --- a/src/soc/mediatek/mt8186/include/soc/mt6366.h +++ b/src/soc/mediatek/mt8186/include/soc/mt6366.h @@ -28,6 +28,9 @@ PMIC_TOP_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, + PMIC_VPROC12_OP_EN = 0x1410, + PMIC_VPROC12_DBG0 = 0x141e, + PMIC_VPROC12_VOSEL = 0x1426, PMIC_VCORE_OP_EN = 0x1490, PMIC_VCORE_DBG0 = 0x149e, PMIC_VCORE_VOSEL = 0x14aa, @@ -37,6 +40,9 @@ PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, PMIC_VDDQ_OP_EN = 0x1b16, + PMIC_VSRAM_PROC12_OP_EN = 0x1b90, + PMIC_VSRAM_PROC12_DBG0 = 0x1ba2, + PMIC_VSRAM_PROC12_VOSEL = 0x1bf0, PMIC_LDO_VMC_CON0 = 0x1cc4, PMIC_LDO_VMC_OP_EN = 0x1cc6, PMIC_LDO_VMCH_CON0 = 0x1cd8, @@ -53,6 +59,8 @@ MT6366_VDDQ, MT6366_VMCH, MT6366_VMC, + MT6366_VPROC12, + MT6366_VSRAM_PROC12, MT6366_REGULATOR_NUM, }; diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index e63a264..406c524 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -493,6 +493,50 @@ udelay(1); } +static u32 pmic_get_vproc12_vol(void) +{ + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VPROC12_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +static void pmic_set_vproc12_vol(u32 v_uv) +{ + u16 vol_reg; + + assert(v_uv >= 500000); + assert(v_uv <= 1293750); + + vol_reg = (v_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VPROC12_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VPROC12_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +static u32 pmic_get_vsram_proc12_vol(void) +{ + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VSRAM_PROC12_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +static void pmic_set_vsram_proc12_vol(u32 v_uv) +{ + u16 vol_reg; + + assert(v_uv >= 500000); + assert(v_uv <= 1293750); + + vol_reg = (v_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VSRAM_PROC12_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VSRAM_PROC12_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + static u32 pmic_get_vdram1_vol(void) { u32 vol_reg; @@ -779,6 +823,12 @@ case MT6366_VMC: pmic_set_vmc_vol(voltage_uv); break; + case MT6366_VPROC12: + pmic_set_vproc12_vol(voltage_uv); + break; + case MT6366_VSRAM_PROC12: + pmic_set_vsram_proc12_vol(voltage_uv); + break; default: printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); break; @@ -798,6 +848,10 @@ return pmic_get_vmch_vol(); case MT6366_VMC: return pmic_get_vmc_vol(); + case MT6366_VPROC12: + return pmic_get_vproc12_vol(); + case MT6366_VSRAM_PROC12: + return pmic_get_vsram_proc12_vol(); default: printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/59566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904 Gerrit-Change-Number: 59566 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021