coreboot-gerrit November 2021

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Change in coreboot[master]: drivers/analogix/anx7625: Fix return code handling
by Yu-Ping Wu (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Yu-Ping Wu. Hello Hung-Te Lin, Wei-Shun Chang, build bot (Jenkins), Xin Ji, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59539 to look at the new patch set (#2). Change subject: drivers/analogix/anx7625: Fix return code handling ...................................................................... drivers/analogix/anx7625: Fix return code handling On some platforms (rockchip, mediatek), platform_i2c_transfer() might return a positive error code, and so are i2c_readb() and i2c_writeb(). Currently the analogix driver incorrectly assumes the error code is always negative. Therefore, fix the return code handling in functions anx7625_reg_*(), log the received return code, and return -1 from them. BUG=b:207055969 TEST=emerge-asurada coreboot BRANCH=none Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 22 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/59539/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Gerrit-Change-Number: 59539 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wei-Shun Chang <weishunc(a)google.com> Gerrit-Reviewer: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Sridhar Siricilla (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Ravindra, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... Patch Set 12: (3 comments) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/55364/comment/2005328c_53df93c6 PS12, Line 145: cse_fw_sync() must be called after DRAM initialization as : * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) : * is expected to be executed after DRAM initialization. > what happen to this recommendation. […] As part of cse_fw_sync(), coreboot sends few commands like GET BOOT PARTITION INFO, SET BOOT PARTITION INFO, HMRFPO ENABLE and GLOBAL RESET commands to CSE in different scenarios. Earlier CSE FW used to support HMRFPO ENABLE after only DRAM Initialization. But, recent CSE FW Version can support HMRFPO ENABLE even before DRAM initialization, hence I am moving up the cse_fw_sync() call before DRAM Init. The earlier advisory is not applicable so I removed it. https://review.coreboot.org/c/coreboot/+/55364/comment/a0c453e6_e9713ed1 PS12, Line 140: > can we add a timestamp around this to know how much time we are really spending for this command if […] We can add, I will push the updated patch. https://review.coreboot.org/c/coreboot/+/55364/comment/91f325ee_c0260461 PS12, Line 142: cse_fw_sync > can you move this call immediately after heci_init() ? Since the cse_fw_sync() is not be run during S3 resume , it has to be after line#130. Since code@line#139 was added recently, so I will move the call after #line 130. -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 09:27:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/*: Enable dGPU temp/fan reporting
by Patrick Georgi (Code Review) 23 Nov '21

23 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59123 ) Change subject: mb/system76/*: Enable dGPU temp/fan reporting ...................................................................... mb/system76/*: Enable dGPU temp/fan reporting Select the EC option on boards with dGPUs to report GPU temperature and fan data. Tested on system76/oryp6. The GPU fan speed is reported in sensors when the system is under load. system76_acpi-acpi-0 Adapter: ACPI interface CPU fan: 1985 RPM GPU fan: 2348 RPM CPU temp: +68.0°C GPU temp: +0.0°C Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59123 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/addw1/Kconfig M src/mainboard/system76/bonw14/Kconfig M src/mainboard/system76/galp5/Kconfig M src/mainboard/system76/gaze15/Kconfig M src/mainboard/system76/gaze16/Kconfig M src/mainboard/system76/oryp5/Kconfig M src/mainboard/system76/oryp6/Kconfig M src/mainboard/system76/oryp8/Kconfig 8 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig index 1c1a614..c307a7d 100644 --- a/src/mainboard/system76/addw1/Kconfig +++ b/src/mainboard/system76/addw1/Kconfig @@ -8,6 +8,7 @@ select EC_SYSTEM76_EC select EC_SYSTEM76_EC_BAT_THRESHOLDS select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU select EC_SYSTEM76_EC_OLED select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/system76/bonw14/Kconfig b/src/mainboard/system76/bonw14/Kconfig index 6f93e09..adbf3c6 100644 --- a/src/mainboard/system76/bonw14/Kconfig +++ b/src/mainboard/system76/bonw14/Kconfig @@ -7,6 +7,7 @@ select EC_SYSTEM76_EC select EC_SYSTEM76_EC_BAT_THRESHOLDS select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/system76/galp5/Kconfig b/src/mainboard/system76/galp5/Kconfig index 534c253..15b2cbd 100644 --- a/src/mainboard/system76/galp5/Kconfig +++ b/src/mainboard/system76/galp5/Kconfig @@ -8,6 +8,7 @@ select DRIVERS_INTEL_USB4_RETIMER select EC_SYSTEM76_EC select EC_SYSTEM76_EC_BAT_THRESHOLDS + select EC_SYSTEM76_EC_DGPU select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig index 6f84e86..7bdfac4 100644 --- a/src/mainboard/system76/gaze15/Kconfig +++ b/src/mainboard/system76/gaze15/Kconfig @@ -7,6 +7,7 @@ select EC_SYSTEM76_EC select EC_SYSTEM76_EC_BAT_THRESHOLDS select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/system76/gaze16/Kconfig b/src/mainboard/system76/gaze16/Kconfig index 90d871e..7b427cd 100644 --- a/src/mainboard/system76/gaze16/Kconfig +++ b/src/mainboard/system76/gaze16/Kconfig @@ -7,6 +7,7 @@ select EC_SYSTEM76_EC select EC_SYSTEM76_EC_BAT_THRESHOLDS select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/system76/oryp5/Kconfig b/src/mainboard/system76/oryp5/Kconfig index 317e29b..1dee8ad 100644 --- a/src/mainboard/system76/oryp5/Kconfig +++ b/src/mainboard/system76/oryp5/Kconfig @@ -8,6 +8,7 @@ select EC_SYSTEM76_EC select EC_SYSTEM76_EC_BAT_THRESHOLDS select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig index b4a5903..246f02b 100644 --- a/src/mainboard/system76/oryp6/Kconfig +++ b/src/mainboard/system76/oryp6/Kconfig @@ -8,6 +8,7 @@ select EC_SYSTEM76_EC select EC_SYSTEM76_EC_BAT_THRESHOLDS select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/system76/oryp8/Kconfig b/src/mainboard/system76/oryp8/Kconfig index 6c9ff4e..aee45be 100644 --- a/src/mainboard/system76/oryp8/Kconfig +++ b/src/mainboard/system76/oryp8/Kconfig @@ -8,6 +8,7 @@ select EC_SYSTEM76_EC select EC_SYSTEM76_EC_BAT_THRESHOLDS select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT -- To view, visit https://review.coreboot.org/c/coreboot/+/59123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7 Gerrit-Change-Number: 59123 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/system76/ec: acpi: Add dGPU thermal reporting
by Patrick Georgi (Code Review) 23 Nov '21

23 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57881 ) Change subject: ec/system76/ec: acpi: Add dGPU thermal reporting ...................................................................... ec/system76/ec: acpi: Add dGPU thermal reporting Add a new config for boards with dGPUs to enable reporting fan duty and temperature. The dGPU is not yet enabled on any boards, so it always reports the temp as 0. However, the EC firmware does use the dGPU's fan and so reports valid information for fan speed. Change-Id: Iae1063ee6a082a77ed026178eb9471bbc2b2fadf Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57881 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/system76/ec/Kconfig M src/ec/system76/ec/acpi/s76.asl 2 files changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/ec/system76/ec/Kconfig b/src/ec/system76/ec/Kconfig index e9b8091..499b7f8 100644 --- a/src/ec/system76/ec/Kconfig +++ b/src/ec/system76/ec/Kconfig @@ -13,6 +13,11 @@ bool default n +config EC_SYSTEM76_EC_DGPU + depends on EC_SYSTEM76_EC + bool + default n + config EC_SYSTEM76_EC_OLED depends on EC_SYSTEM76_EC bool diff --git a/src/ec/system76/ec/acpi/s76.asl b/src/ec/system76/ec/acpi/s76.asl index 62a93ba..d641ada 100644 --- a/src/ec/system76/ec/acpi/s76.asl +++ b/src/ec/system76/ec/acpi/s76.asl @@ -117,6 +117,9 @@ Method (NFAN, 0, Serialized) { Return (Package() { "CPU fan", +#if CONFIG(EC_SYSTEM76_EC_DGPU) + "GPU fan", +#endif }) } @@ -144,6 +147,9 @@ Method (NTMP, 0, Serialized) { Return (Package() { "CPU temp", +#if CONFIG(EC_SYSTEM76_EC_DGPU) + "GPU temp", +#endif }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/57881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae1063ee6a082a77ed026178eb9471bbc2b2fadf Gerrit-Change-Number: 57881 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/*: Disable IME by CMOS option
by Patrick Georgi (Code Review) 23 Nov '21

23 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57621 ) Change subject: mb/system76/*: Disable IME by CMOS option ...................................................................... mb/system76/*: Disable IME by CMOS option Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H, and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER. The HECI device must be enabled in devicetree for switching modes to function correctly. Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/addw1/cmos.default M src/mainboard/system76/addw1/cmos.layout M src/mainboard/system76/bonw14/cmos.default M src/mainboard/system76/bonw14/cmos.layout M src/mainboard/system76/cml-u/cmos.default M src/mainboard/system76/cml-u/cmos.layout M src/mainboard/system76/darp7/cmos.default M src/mainboard/system76/darp7/cmos.layout M src/mainboard/system76/galp5/cmos.default M src/mainboard/system76/galp5/cmos.layout M src/mainboard/system76/gaze15/cmos.default M src/mainboard/system76/gaze15/cmos.layout M src/mainboard/system76/gaze16/cmos.default M src/mainboard/system76/gaze16/cmos.layout M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/lemp10/cmos.default M src/mainboard/system76/lemp10/cmos.layout M src/mainboard/system76/lemp9/cmos.default M src/mainboard/system76/lemp9/cmos.layout M src/mainboard/system76/oryp5/cmos.default M src/mainboard/system76/oryp5/cmos.layout M src/mainboard/system76/oryp6/cmos.default M src/mainboard/system76/oryp6/cmos.layout M src/mainboard/system76/oryp8/cmos.default M src/mainboard/system76/oryp8/cmos.layout M src/mainboard/system76/oryp8/devicetree.cb M src/mainboard/system76/whl-u/cmos.default M src/mainboard/system76/whl-u/cmos.layout M src/mainboard/system76/whl-u/devicetree.cb 29 files changed, 85 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/addw1/cmos.default b/src/mainboard/system76/addw1/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/addw1/cmos.default +++ b/src/mainboard/system76/addw1/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/addw1/cmos.layout b/src/mainboard/system76/addw1/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/addw1/cmos.layout +++ b/src/mainboard/system76/addw1/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/bonw14/cmos.default b/src/mainboard/system76/bonw14/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/bonw14/cmos.default +++ b/src/mainboard/system76/bonw14/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/bonw14/cmos.layout b/src/mainboard/system76/bonw14/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/bonw14/cmos.layout +++ b/src/mainboard/system76/bonw14/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/cml-u/cmos.default b/src/mainboard/system76/cml-u/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/cml-u/cmos.default +++ b/src/mainboard/system76/cml-u/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/cml-u/cmos.layout b/src/mainboard/system76/cml-u/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/cml-u/cmos.layout +++ b/src/mainboard/system76/cml-u/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/darp7/cmos.default b/src/mainboard/system76/darp7/cmos.default index 06b0433..62715bc 100644 --- a/src/mainboard/system76/darp7/cmos.default +++ b/src/mainboard/system76/darp7/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Enable diff --git a/src/mainboard/system76/darp7/cmos.layout b/src/mainboard/system76/darp7/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/darp7/cmos.layout +++ b/src/mainboard/system76/darp7/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/galp5/cmos.default b/src/mainboard/system76/galp5/cmos.default index 06b0433..62715bc 100644 --- a/src/mainboard/system76/galp5/cmos.default +++ b/src/mainboard/system76/galp5/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Enable diff --git a/src/mainboard/system76/galp5/cmos.layout b/src/mainboard/system76/galp5/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/galp5/cmos.layout +++ b/src/mainboard/system76/galp5/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/gaze15/cmos.default b/src/mainboard/system76/gaze15/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/gaze15/cmos.default +++ b/src/mainboard/system76/gaze15/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/gaze15/cmos.layout b/src/mainboard/system76/gaze15/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/gaze15/cmos.layout +++ b/src/mainboard/system76/gaze15/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/gaze16/cmos.default b/src/mainboard/system76/gaze16/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/gaze16/cmos.default +++ b/src/mainboard/system76/gaze16/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/gaze16/cmos.layout b/src/mainboard/system76/gaze16/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/gaze16/cmos.layout +++ b/src/mainboard/system76/gaze16/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index 29eb3e3..380bdc0 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -125,7 +125,9 @@ device i2c 15 on end end end - device ref heci1 on end + device ref heci1 on + register "HeciEnabled" = "1" + end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/lemp10/cmos.default b/src/mainboard/system76/lemp10/cmos.default index 06b0433..62715bc 100644 --- a/src/mainboard/system76/lemp10/cmos.default +++ b/src/mainboard/system76/lemp10/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Enable diff --git a/src/mainboard/system76/lemp10/cmos.layout b/src/mainboard/system76/lemp10/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/lemp10/cmos.layout +++ b/src/mainboard/system76/lemp10/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/lemp9/cmos.default b/src/mainboard/system76/lemp9/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/lemp9/cmos.default +++ b/src/mainboard/system76/lemp9/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/lemp9/cmos.layout b/src/mainboard/system76/lemp9/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/lemp9/cmos.layout +++ b/src/mainboard/system76/lemp9/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/oryp5/cmos.default b/src/mainboard/system76/oryp5/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/oryp5/cmos.default +++ b/src/mainboard/system76/oryp5/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/oryp5/cmos.layout b/src/mainboard/system76/oryp5/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/oryp5/cmos.layout +++ b/src/mainboard/system76/oryp5/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/oryp6/cmos.default b/src/mainboard/system76/oryp6/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/oryp6/cmos.default +++ b/src/mainboard/system76/oryp6/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/oryp6/cmos.layout b/src/mainboard/system76/oryp6/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/oryp6/cmos.layout +++ b/src/mainboard/system76/oryp6/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/oryp8/cmos.default b/src/mainboard/system76/oryp8/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/oryp8/cmos.default +++ b/src/mainboard/system76/oryp8/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/oryp8/cmos.layout b/src/mainboard/system76/oryp8/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/oryp8/cmos.layout +++ b/src/mainboard/system76/oryp8/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index cd2e617..429ad62 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -160,7 +160,9 @@ device i2c 2c on end end end - device ref heci1 on end + device ref heci1 on + register "HeciEnabled" = "1" + end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/whl-u/cmos.default b/src/mainboard/system76/whl-u/cmos.default index 06b0433..0d37675 100644 --- a/src/mainboard/system76/whl-u/cmos.default +++ b/src/mainboard/system76/whl-u/cmos.default @@ -1,2 +1,3 @@ boot_option=Fallback debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/whl-u/cmos.layout b/src/mainboard/system76/whl-u/cmos.layout index ac81752..a53c3f4 100644 --- a/src/mainboard/system76/whl-u/cmos.layout +++ b/src/mainboard/system76/whl-u/cmos.layout @@ -12,10 +12,15 @@ 400 8 r 0 century 412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter 984 16 h 0 check_sum enumerations +2 0 Enable +2 1 Disable + 4 0 Fallback 4 1 Normal diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 3e28a16..63a9016 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -98,7 +98,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection -- To view, visit https://review.coreboot.org/c/coreboot/+/57621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Gerrit-Change-Number: 57621 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: remove tmp bar assignment for cpu crashlog
by Patrick Georgi (Code Review) 23 Nov '21

23 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59355 ) Change subject: soc/intel/alderlake: remove tmp bar assignment for cpu crashlog ...................................................................... soc/intel/alderlake: remove tmp bar assignment for cpu crashlog When the cpu_cl_discovery is called, coreboot actually assigns a BAR to cpu crashlog pci device. Hence, we don't need to assign a tmp BAR for cpu crashlog pci device BUG=b:195327879 TEST=Found BERT table is created and the tcss function is ok in depthcharge Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59355 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/crashlog.c 1 file changed, 2 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c index 9435aa0..3a857c1 100644 --- a/src/soc/intel/alderlake/crashlog.c +++ b/src/soc/intel/alderlake/crashlog.c @@ -210,27 +210,14 @@ m_cpu_crashLog_support = true; - /* Program BAR address and enable command register memory space decoding */ - u32 tmp_bar_addr = PCH_PWRM_BASE_ADDRESS; - printk(BIOS_DEBUG, "tmp_bar_addr: 0x%X\n", tmp_bar_addr); - - if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { - pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, tmp_bar_addr); - } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { - pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, tmp_bar_addr); - } else { - printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n", - cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); - return false; - } - pci_or_config16(SA_DEV_TMT, PCI_COMMAND, PCI_COMMAND_MEMORY); + const struct resource *res = find_resource(SA_DEV_TMT, PCI_BASE_ADDRESS_0); + printk(BIOS_DEBUG, "cpu crashlog bar addr: 0x%llX\n", res->base); if (!cpu_cl_gen_discovery_table()) { printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n"); m_cpu_crashLog_present = false; return false; } - m_cpu_crashLog_present = true; return true; } -- To view, visit https://review.coreboot.org/c/coreboot/+/59355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be Gerrit-Change-Number: 59355 Gerrit-PatchSet: 10 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/redrix: Disable autonomous GPIO power management
by Patrick Georgi (Code Review) 23 Nov '21

23 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58694 ) Change subject: mb/google/brya/var/redrix: Disable autonomous GPIO power management ...................................................................... mb/google/brya/var/redrix: Disable autonomous GPIO power management With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully. BUG=b:202246591 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage. Change-Id: Idc01ebb4d3ef990f24f18bef5424b7d6ba683d49 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58694 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 10 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 878fd56..67cb7f3 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -31,8 +31,17 @@ end end chip soc/intel/alderlake + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" - register "CnviBtAudioOffload" = "true" # FIVR RFI Spread Spectrum 6% register "FivrSpreadSpectrum" = "FIVR_SS_6" -- To view, visit https://review.coreboot.org/c/coreboot/+/58694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc01ebb4d3ef990f24f18bef5424b7d6ba683d49 Gerrit-Change-Number: 58694 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: emulation/qemu-i440fx,q35: avoid writing to ROM
by Patrick Georgi (Code Review) 23 Nov '21

23 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59474 ) Change subject: emulation/qemu-i440fx,q35: avoid writing to ROM ...................................................................... emulation/qemu-i440fx,q35: avoid writing to ROM libcbfs has a workaround to avoid writing to ROM areas: /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { This workaround is not triggered in QEMU, because BOOT_DEVICE_MEMORY_MAPPED is only selected for SPI boot devices. This results in confusing (to the VMM developer) writes to read-only memory. As far as I can tell, this issue is weird but harmless, because the code does memcpy to ROM with source == destination. The concensus in the mailing list thread [1] was that it's worthwhile to be fixed regardless. [1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/KDI… Change-Id: I5cefbc31f917021236105f7dc969118d612ac399 Signed-off-by: Julian Stecklina <julian.stecklina(a)cyberus-technology.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59474 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index dd11092..436bb20 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -16,6 +16,7 @@ select HAVE_ASAN_IN_ROMSTAGE select NO_SMM select BOOT_DEVICE_NOT_SPI_FLASH + select BOOT_DEVICE_MEMORY_MAPPED config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 155540d..1fc82b5 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_CHROMEOS select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select BOOT_DEVICE_NOT_SPI_FLASH + select BOOT_DEVICE_MEMORY_MAPPED config VBOOT select VBOOT_MUST_REQUEST_DISPLAY 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cefbc31f917021236105f7dc969118d612ac399 Gerrit-Change-Number: 59474 Gerrit-PatchSet: 3 Gerrit-Owner: Julian Stecklina Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Peter Stuge <peter(a)stuge.se> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/trogdor: change pin define for quackingstick
by Patrick Georgi (Code Review) 23 Nov '21

23 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59533 ) Change subject: mb/google/trogdor: change pin define for quackingstick ...................................................................... mb/google/trogdor: change pin define for quackingstick change TP_EN pin to GPIO_67 for quackingstick BUG=b:206862167 BRANCH=trogdor TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59533 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Bob Moragues <moragues(a)google.com> --- M src/mainboard/google/trogdor/board.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Bob Moragues: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index 534cfe9..7245743 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -23,7 +23,7 @@ #define GPIO_AVDD_LCD_ENABLE GPIO(88) #define GPIO_AVEE_LCD_ENABLE GPIO(21) #define GPIO_VDD_RESET_1V8 GPIO(87) -#define GPIO_TP_EN GPIO(85) +#define GPIO_TP_EN (CONFIG(BOARD_GOOGLE_QUACKINGSTICK) ? GPIO(67) : GPIO(85)) #define GPIO_EDP_BRIDGE_ENABLE dead_code_t(gpio_t) #define GPIO_EN_PP3300_DX_EDP dead_code_t(gpio_t) #define GPIO_PS8640_EDP_BRIDGE_PD_L dead_code_t(gpio_t) -- To view, visit https://review.coreboot.org/c/coreboot/+/59533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0 Gerrit-Change-Number: 59533 Gerrit-PatchSet: 2 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750
by Patrick Georgi (Code Review) 23 Nov '21

23 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59429 ) Change subject: drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750 ...................................................................... drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750 The device is a PCIe Gen1 to SD 3.0 card reader controller to be used in the Chromebook. The datasheet name is GL9750S and the revision is 01. The patch disables ASPM L0s. BUG=b:206014046 TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts. Signed-off-by: Ben Chuang <benchuanggli(a)gmail.com> Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/drivers/genesyslogic/gl9750/Kconfig A src/drivers/genesyslogic/gl9750/Makefile.inc A src/drivers/genesyslogic/gl9750/gl9750.c A src/drivers/genesyslogic/gl9750/gl9750.h M src/include/device/pci_ids.h 5 files changed, 74 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/genesyslogic/gl9750/Kconfig b/src/drivers/genesyslogic/gl9750/Kconfig new file mode 100644 index 0000000..f3449b0 --- /dev/null +++ b/src/drivers/genesyslogic/gl9750/Kconfig @@ -0,0 +1,8 @@ +config DRIVERS_GENESYSLOGIC_GL9750 + bool "Genesys Logic GL9750" + help + GL9750 is a PCI Express Rev. 1.1 compliant card reader controller + which integrates PCI Express PHY, memory card access interface, + regulators (3.3V-to-1.2V) and card power switch. Enabling this driver + will disable L0s support, which will allow the device to enter the + PCIe L1 link state. diff --git a/src/drivers/genesyslogic/gl9750/Makefile.inc b/src/drivers/genesyslogic/gl9750/Makefile.inc new file mode 100644 index 0000000..0f771cc --- /dev/null +++ b/src/drivers/genesyslogic/gl9750/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENESYSLOGIC_GL9750) += gl9750.c diff --git a/src/drivers/genesyslogic/gl9750/gl9750.c b/src/drivers/genesyslogic/gl9750/gl9750.c new file mode 100644 index 0000000..ca5cd09 --- /dev/null +++ b/src/drivers/genesyslogic/gl9750/gl9750.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for Genesys Logic GL9750 */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include "gl9750.h" + +static void gl9750_enable(struct device *dev) +{ + printk(BIOS_INFO, "GL9750: configure ASPM\n"); + + /* Set Vendor Config to be configurable */ + pci_or_config32(dev, CFG, CFG_EN); + + /* + * When both ASPM L0s and L1 are supported, GL9750 may not enter L1. + * So disable L0s support. + */ + pci_and_config32(dev, CFG2, ~CFG2_L0S_SUPPORT); + + /* Set Vendor Config to be non-configurable */ + pci_and_config32(dev, CFG, ~CFG_EN); +} + +static struct device_operations gl9750_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .enable = gl9750_enable +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_GLI_9750, + 0 +}; + +static const struct pci_driver genesyslogic_gl9750 __pci_driver = { + .ops = &gl9750_ops, + .vendor = PCI_VENDOR_ID_GLI, + .devices = pci_device_ids, +}; + +struct chip_operations drivers_generic_genesyslogic_gl9750_ops = { + CHIP_NAME("Genesys Logic GL9750") +}; diff --git a/src/drivers/genesyslogic/gl9750/gl9750.h b/src/drivers/genesyslogic/gl9750/gl9750.h new file mode 100644 index 0000000..e446cae --- /dev/null +++ b/src/drivers/genesyslogic/gl9750/gl9750.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DRIVERS_GENESYSLOGIC_GL9750_H +#define DRIVERS_GENESYSLOGIC_GL9750_H + +/* Definitions for Genesys Logic GL9750 */ + +#define CFG 0x800 +#define CFG_EN 0x1 +#define CFG2 0x848 +#define CFG2_L0S_SUPPORT (0x1 << 6) + +#endif /* DRIVERS_GENESYSLOGIC_GL9750_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c6ef121..fc82c26 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2064,8 +2064,9 @@ #define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea #define PCI_VENDOR_ID_GLI 0x17a0 -#define PCI_DEVICE_ID_GLI_9763E 0xe763 +#define PCI_DEVICE_ID_GLI_9750 0x9750 #define PCI_DEVICE_ID_GLI_9755 0x9755 +#define PCI_DEVICE_ID_GLI_9763E 0xe763 #define PCI_VENDOR_ID_XGI 0x18ca #define PCI_DEVICE_ID_XGI_20 0x0020 -- To view, visit https://review.coreboot.org/c/coreboot/+/59429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c Gerrit-Change-Number: 59429 Gerrit-PatchSet: 4 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Greg Tu <greg.tu(a)genesyslogic.com.tw> Gerrit-CC: HsuanYang Chen <ynop77(a)gmail.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit November 2021