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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#14).
Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions
......................................................................
mb/google/brya/var/baseboard/brask: Add power limits functions
Copy function variant_update_power_limits from brya to set power limits.
Add function variant_update_psys_power_limits and copy the algorithm
from puff. Add structure system_power_limits and psys_config to define
and config the psys power limits.
BUG=b:193864533
BRANCH=none
TEST=Build Pass
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248
---
M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
A src/mainboard/google/brya/variants/baseboard/brask/ramstage.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
3 files changed, 172 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/58241/14
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Change subject: mb/google/brya/var/primus: Update thermal table for primus
......................................................................
Patch Set 8: Code-Review+1
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59574 )
Change subject: [DO NOT SUBMIT] Doc/gfx/libgfxinit.md: Add info about display engine
......................................................................
[DO NOT SUBMIT] Doc/gfx/libgfxinit.md: Add info about display engine
Add a section about the display engine, the main thing libgfxinit
concerns itself with.
Currently, this is just a backup of things I said on IRC. Obviously,
this is not yet ready for review.
Change-Id: I8690edea782b9ac13d1588c791b297e140df7e90
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Documentation/gfx/libgfxinit.md
1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59574/1
diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md
index 40f194a..d17e364 100644
--- a/Documentation/gfx/libgfxinit.md
+++ b/Documentation/gfx/libgfxinit.md
@@ -16,6 +16,27 @@
from Arrandale to Coffee Lake, and Apollo Lake are verified to work
within *coreboot*.
+General idea
+------------
+
+for libgfxinit, the important part is the display engine. we don't really care about GPU stuff (render engine, 3D, shaders...), we just want to "pipe" the framebuffer data to one or more monitors
+I see the display engine as the "pipe dream" part of the hardware: it's processing possibly endless streams of data, routing them from the sources (framebuffers) to the destinations (physical ports, e.g. VGA, DVI, HDMI, DP, LVDS, eDP, MIPI DSI...)
+and with "pipe dream" I imagine something like this, but simpler and more organized: [Video of Windows XP 3D pipes screensaver](https://www.youtube.com/watch?v=MKqrLGFoK9E)
+the idea of pipes is similar to Unix shell pipelines: <https://en.wikipedia.org/wiki/Pipeline_(Unix)>
+hmmm, IIRC Intel hardware has some specific part called "pipe". I'm referring to the entire display engine, how the various hardware units are connected. I'll use "pipelines" from now on to avoid any potential confusion
+
+display engine pipelines are pretty much the same idea as Unix pipelines, but in hardware
+here's the display engine block diagram of haswell/lynxpoint: ["Haswell Display Connections" figure from PRM Volume 11a: Display (Haswell)"](https://imgur.com/DVREcHS.png)
+the equivalent of "programs" in Unix pipelines would be the hardware blocks: pipe X, panel fitting, transcoder X, DDI X...
+because hardware is hard, there aren't many ways to connect the blocks (with Unix shell pipelines, you can connect anything to anything, even if it won't work)
+to choose how blocks are connected, the display engine has muxes (multiplexers): https://en.wikipedia.org/wiki/Multiplexer
+Haswell has a dedicated eDP mux and a "Cross Point Mux & Multi-stream" block for the other DDIs (DDI = Digital Display Interface)
+the latter block allows connecting the output of any transcoder to any DDI, and also allows connecting multiple transcoder outputs to the same DDI (needed for DisplayPort Multi Stream Transport)
+
+also, note the following route: Memory/Config interface ---> Pipe A ---> eDP Mux ---> Transcoder eDP ---> DDI A
+that route doesn't use any blocks in the Power Down Well (gray regions). this allows powering down parts of the display engine to save power
+this is very convenient for laptops: in most cases, only the integrated eDP LCD is used when running off battery power
+
GMA: Framebuffer Configuration
------------------------------
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Peter Ou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59091 )
Change subject: mb/google/brya/var/kano: set power limits for thermal
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59091/comment/f3215c1a_daade847
PS1, Line 12: build pass
> Hi Peter, could you share test results with power limits value to issue 205648035 for reference here […]
Hi Sumeet
the power limit setting we verify in A stage for reference, we will verify again in next stage (EVT) and provide the test result for reference.
File src/mainboard/google/brya/variants/kano/ramstage.c:
https://review.coreboot.org/c/coreboot/+/59091/comment/ed2dc52f_7a2aec22
PS1, Line 8: bug:191906315 comment #10
> Can you check if performance config values suits your system design and battery specs ?
Base on thermal test result in A stage, both of the different setting can meet customer's requirement, we also need to verify in EVT/DVT stage to check the performance behavior.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 )
Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
......................................................................
Patch Set 12:
(2 comments)
File src/soc/intel/alderlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/55364/comment/381c0fb2_8546c0cf
PS12, Line 145: cse_fw_sync() must be called after DRAM initialization as
: * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())
: * is expected to be executed after DRAM initialization.
> As part of cse_fw_sync(), coreboot sends few commands like GET BOOT PARTITION INFO, SET BOOT PARTITI […]
Thanks for explanation and can you please write the same to the commit msg for record so folks don't run into issue while integration latest code with older binary (if any?)
https://review.coreboot.org/c/coreboot/+/55364/comment/43c41d11_bccfc794
PS12, Line 140:
> We can add, I will push the updated patch.
Ack
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Alan Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59573 )
Change subject: test
......................................................................
test
Change-Id: I34e9fe753934b3fc4c44273fab9d579d03929f8e
---
A test
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/59573/1
diff --git a/test b/test
new file mode 100644
index 0000000..9daeafb
--- /dev/null
+++ b/test
@@ -0,0 +1 @@
+test
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58241
to look at the new patch set (#13).
Change subject: mb/google/brya/variants/brask: Set PL and PsysPL
......................................................................
mb/google/brya/variants/brask: Set PL and PsysPL
Copy function variant_update_power_limits from brya to set power limits.
Add function variant_update_psys_power_limits and copy the algorithm
from puff. Add structure system_power_limits and psys_config to define
and config the psys power limits.
BUG=b:193864533
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248
---
M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
A src/mainboard/google/brya/variants/baseboard/brask/ramstage.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/brya/variants/brask/Makefile.inc
A src/mainboard/google/brya/variants/brask/ramstage.c
5 files changed, 234 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/58241/13
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Change subject: drivers/analogix/anx7625: Fix edid_read()
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59540/comment/d588841a_800344c3
PS1, Line 12: ic
> is
Done
https://review.coreboot.org/c/coreboot/+/59540/comment/54f3b527_a0db3542
PS1, Line 20: kernel
> Please mention the version.
Done
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Change subject: drivers/analogix/anx7625: Fix return code handling
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59539/comment/dc2e8881_0c87f2cf
PS1, Line 13: anx7625_reg_*(), and return -1 from them.
> … and log the received return code.
Done
Patchset:
PS1:
> BRANCH should be none or asurada?
Because there's no practical impact on asurada, I didn't plan to cherry pick this to fw branch. That would introduce extra risk instead.
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Hello Hung-Te Lin, Wei-Shun Chang, build bot (Jenkins), Paul Menzel, Xin Ji,
I'd like you to reexamine a change. Please visit
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Change subject: drivers/analogix/anx7625: Fix edid_read()
......................................................................
drivers/analogix/anx7625: Fix edid_read()
The current implementations of edid_read() and segments_edid_read() have
a few problems:
1. The type of variable `c` is incorrect, not matching the return type
of sp_tx_aux_rd(). In addition, the meaning of `c` is unknown.
2. It is pointless to do `cnt++` when sp_tx_aux_rd() fails.
3. These two functions ignore the return value of
anx7625_reg_block_read().
4. In segments_edid_read(), anx7625_reg_write() might return a positive
value on failure.
Fix all of the 4 issues, and modify the code to be closer to kernel
5.10's implementation (drivers/gpu/drm/bridge/analogix/anx7625.c). Note
that, however, unlike in kernel, anx7625_reg_block_read() here doesn't
return the number of bytes. On success, 0 is returned instead.
In addition, change the return value to -1 for edid_read() and
segments_edid_read() on failure.
BUG=b:207055969
TEST=emerge-asurada coreboot
BRANCH=none
Change-Id: Ife9d7d97df2926b4581ba519a152c9efed8cd969
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/drivers/analogix/anx7625/anx7625.c
1 file changed, 26 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/59540/2
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