coreboot-gerrit November 2021

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Change in coreboot[master]: amdfwtool: merge lookup table to psp fw table
by Kangheui Won (Code Review) 23 Nov '21

23 Nov '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59584 ) Change subject: amdfwtool: merge lookup table to psp fw table ...................................................................... amdfwtool: merge lookup table to psp fw table Merge psp_dir_valid_entries into amd_psp_fw_table. PSPBTLDR_WL_FILE and PSPBTLDR_AB_FILE needs additional logic since both points to the same firmware entry and which one to include depends on commandline option. BUG=b:206909680 TEST=build guybrush and confirm amdfw and coreboot.rom are identical Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I552240e53fa0e2f8bef5026e007c8b54458bd656 --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 115 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/59584/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 957c81e..6e663ae 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -220,54 +220,100 @@ } amd_fw_entry amd_psp_fw_table[] = { - { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, - { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, + { .fw_name = "AMD_PUBKEY_FILE", + .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, + { .fw_name = "PSPBTLDR_FILE", + .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, + { .fw_name = "PSP_SMUFW1_SUB0_FILE", + .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, + { .fw_name = "PSPRCVR_FILE", + .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, + { .fw_name = "PUBSIGNEDKEY_FILE", + .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, + { .fw_name = "PSPSECUREOS_FILE", + .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 }, + { .fw_name = "PSPNVRAM_FILE", + .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 }, + { .fw_name = "PSP_SMUFW1_SUB2_FILE", + .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH }, + { .fw_name = "PSPSECUREDEBUG_FILE", + .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 }, + { .fw_name = "PSPTRUSTLETS_FILE", + .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 }, + { .fw_name = "TRUSTLETKEY_FILE", + .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 }, + { .fw_name = "PSP_SMUFW2_SUB2_FILE", + .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH }, + { .fw_name = "PSP_SMUFW1_SUB1_FILE", + .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, + { .fw_name = "PSP_SMUFW2_SUB1_FILE", + .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, + { .fw_name = "PSP_SMUFW2_SUB0_FILE", + .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH }, + { .fw_name = "SMUSCS_FILE", + .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 }, - { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 }, - { .type = AMD_HW_IPCFG, .level = PSP_LVL2 }, - { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH }, + { .fw_name = "PSP_SEC_DEBUG_FILE", + .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 }, + { .fw_name = "PSP_HW_IPCFG_FILE", + .type = AMD_HW_IPCFG, .level = PSP_LVL2 }, + { .fw_name = "PSP_IKEK_FILE", + .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH }, { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH }, - { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH }, - { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH }, - { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH }, - { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 }, - { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 }, - { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 }, - { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 }, - { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2}, - { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 }, - { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH }, - { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH }, - { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 }, - { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 }, - { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH }, - { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 }, - { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 }, - { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 }, - { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 }, - { .type = AMD_ABL0, .level = PSP_BOTH }, - { .type = AMD_ABL1, .level = PSP_BOTH }, - { .type = AMD_ABL2, .level = PSP_BOTH }, - { .type = AMD_ABL3, .level = PSP_BOTH }, - { .type = AMD_ABL4, .level = PSP_BOTH }, - { .type = AMD_ABL5, .level = PSP_BOTH }, - { .type = AMD_ABL6, .level = PSP_BOTH }, - { .type = AMD_ABL7, .level = PSP_BOTH }, + { .fw_name = "PSP_SECG0_FILE", + .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH }, + { .fw_name = "PSP_SECG2_FILE", + .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH }, + { .fw_name = "PSP_SECG1_FILE", + .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH }, + { .fw_name = "PSP_MP2FW2_FILE", + .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 }, + { .fw_name = "PSP_MP2FW1_FILE", + .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 }, + { .fw_name = "PSP_MP2FW0_FILE", + .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 }, + { .fw_name = "AMD_DRIVER_ENTRIES", + .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 }, + { .fw_name = "PSP_KVM_ENGINE_DUMMY_FILE", + .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 }, + { .fw_name = "PSP_S0I3_FILE", + .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 }, + { .fw_name = "VBIOS_BTLOADER_FILE", + .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH }, + { .fw_name = "SECURE_POLICY_L1_FILE", + .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH }, + { .fw_name = "UNIFIEDUSB_FILE", + .type = AMD_FW_USB_PHY, .level = PSP_LVL2 }, + { .fw_name = "DRTMTA_FILE", + .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 }, + { .fw_name = "KEYDBBL_FILE", + .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH }, + { .fw_name = "KEYDB_TOS_FILE", + .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 }, + { .fw_name = "DMCUERAMDCN21_FILE", + .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 }, + { .fw_name = "DMCUINTVECTORSDCN21_FILE", + .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 }, + { .fw_name = "RPMC_FILE", + .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 }, + { .fw_name = "PSPBTLDR_AB_FILE", + .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 }, + { .fw_name = "PSP_ABL0_FILE", + .type = AMD_ABL0, .level = PSP_BOTH }, + { .fw_name = "PSP_ABL1_FILE", + .type = AMD_ABL1, .level = PSP_BOTH }, + { .fw_name = "PSP_ABL2_FILE", + .type = AMD_ABL2, .level = PSP_BOTH }, + { .fw_name = "PSP_ABL3_FILE", + .type = AMD_ABL3, .level = PSP_BOTH }, + { .fw_name = "PSP_ABL4_FILE", + .type = AMD_ABL4, .level = PSP_BOTH }, + { .fw_name = "PSP_ABL5_FILE", + .type = AMD_ABL5, .level = PSP_BOTH }, + { .fw_name = "PSP_ABL6_FILE", + .type = AMD_ABL6, .level = PSP_BOTH }, + { .fw_name = "PSP_ABL7_FILE", + .type = AMD_ABL7, .level = PSP_BOTH }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH }, diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index a7ac7c1..203e960 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -213,6 +213,7 @@ #define PSP_LVL2 (1 << 1) #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) typedef struct _amd_fw_entry { + const char *fw_name; amd_fw_type type; char *filename; uint8_t subprog; diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 25e739a..9dd0272 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <commonlib/helpers.h> #include <stdio.h> #include <regex.h> #include <string.h> @@ -101,64 +100,7 @@ extern amd_fw_entry amd_psp_fw_table[]; extern amd_bios_entry amd_bios_table[]; -struct psp_valid_entry_table { - const char *fw_name; - amd_fw_type fw_type; - uint8_t subprog; -}; - -static const struct psp_valid_entry_table psp_dir_valid_entries[] = { - {"PSPBTLDR_WL_FILE", AMD_FW_PSP_BOOTLOADER_AB, 0}, - {"PSPBTLDR_FILE", AMD_FW_PSP_BOOTLOADER, 0}, - {"AMD_PUBKEY_FILE", AMD_FW_PSP_PUBKEY, 0}, - {"PSPRCVR_FILE", AMD_FW_PSP_RECOVERY, 0}, - {"PUBSIGNEDKEY_FILE", AMD_FW_PSP_RTM_PUBKEY, 0}, - {"PSPNVRAM_FILE", AMD_FW_PSP_NVRAM, 0}, - {"SMUSCS_FILE", AMD_FW_PSP_SMUSCS, 0}, - {"PSPTRUSTLETS_FILE", AMD_FW_PSP_TRUSTLETS, 0}, - {"PSPSECUREDEBUG_FILE", AMD_FW_PSP_SECURED_DEBUG, 0}, - {"PSP_SMUFW1_SUB0_FILE", AMD_FW_PSP_SMU_FIRMWARE, 0}, - {"PSP_HW_IPCFG_FILE", AMD_HW_IPCFG, 0}, - {"PSP_SMUFW1_SUB1_FILE", AMD_FW_PSP_SMU_FIRMWARE, 1}, - {"PSP_SMUFW1_SUB2_FILE", AMD_FW_PSP_SMU_FIRMWARE, 2}, - {"PSP_SMUFW2_SUB0_FILE", AMD_FW_PSP_SMU_FIRMWARE2, 0}, - {"PSP_SMUFW2_SUB1_FILE", AMD_FW_PSP_SMU_FIRMWARE2, 1}, - {"PSP_SMUFW2_SUB2_FILE", AMD_FW_PSP_SMU_FIRMWARE2, 2}, - {"PSP_SEC_DEBUG_FILE", AMD_DEBUG_UNLOCK, 0}, - {"PSP_ABL0_FILE", AMD_ABL0, 0}, - {"PSP_ABL1_FILE", AMD_ABL1, 0}, - {"PSP_ABL2_FILE", AMD_ABL2, 0}, - {"PSP_ABL3_FILE", AMD_ABL3, 0}, - {"PSP_ABL4_FILE", AMD_ABL4, 0}, - {"PSP_ABL5_FILE", AMD_ABL5, 0}, - {"PSP_ABL6_FILE", AMD_ABL6, 0}, - {"PSP_ABL7_FILE", AMD_ABL7, 0}, - {"PSPSECUREOS_FILE", AMD_FW_PSP_SECURED_OS, 0}, - {"TRUSTLETKEY_FILE", AMD_FW_PSP_TRUSTLETKEY, 0}, - {"PSP_IKEK_FILE", AMD_WRAPPED_IKEK, 0}, - {"PSP_SECG0_FILE", AMD_SEC_GASKET, 0}, - {"PSP_SECG1_FILE", AMD_SEC_GASKET, 1}, - {"PSP_SECG2_FILE", AMD_SEC_GASKET, 2}, - {"PSP_MP2FW0_FILE", AMD_MP2_FW, 0}, - {"PSP_MP2FW1_FILE", AMD_MP2_FW, 1}, - {"PSP_MP2FW2_FILE", AMD_MP2_FW, 2}, - {"PSP_S0I3_FILE", AMD_S0I3_DRIVER, 0}, - {"AMD_DRIVER_ENTRIES", AMD_DRIVER_ENTRIES, 0}, - {"VBIOS_BTLOADER_FILE", AMD_VBIOS_BTLOADER, 0}, - {"SECURE_POLICY_L1_FILE", AMD_FW_TOS_SEC_POLICY, 0}, - {"UNIFIEDUSB_FILE", AMD_FW_USB_PHY, 0}, - {"DRTMTA_FILE", AMD_FW_DRTM_TA, 0}, - {"KEYDBBL_FILE", AMD_FW_KEYDB_BL, 0}, - {"KEYDB_TOS_FILE", AMD_FW_KEYDB_TOS, 0}, - {"DMCUERAMDCN21_FILE", AMD_FW_DMCU_ERAM, 0}, - {"DMCUINTVECTORSDCN21_FILE", AMD_FW_DMCU_ISR, 0}, - {"PSP_KVM_ENGINE_DUMMY_FILE", AMD_FW_KVM_IMAGE, 0}, - {"RPMC_FILE", AMD_RPMC_NVRAM, 0}, - {"PSPBTLDR_AB_FILE", AMD_FW_PSP_BOOTLOADER_AB, 0} -}; - -static bool should_skip_entry(char *fw_name, amd_fw_type fw_type, - amd_cb_config *cb_config) +static bool should_skip_entry(amd_fw_type fw_type, amd_cb_config *cb_config) { switch (fw_type) { case AMD_FW_PSP_SECURED_DEBUG: @@ -172,13 +114,6 @@ return !(cb_config->load_mp2_fw); case AMD_S0I3_DRIVER: return !(cb_config->s0i3); - case AMD_FW_PSP_BOOTLOADER_AB: - if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { - return !(cb_config->have_whitelist); - } else { - return (cb_config->have_whitelist); - } - break; default: /* default to include */ return 0; @@ -190,33 +125,38 @@ { amd_fw_type fw_type = AMD_FW_INVALID; amd_fw_entry *psp_tableptr; - uint8_t subprog = 0; - unsigned long i = 0; + char *tmp = fw_name; - for (i = 0; i < ARRAY_SIZE(psp_dir_valid_entries); i++) { - if (strcmp(fw_name, psp_dir_valid_entries[i].fw_name) == 0) { - fw_type = psp_dir_valid_entries[i].fw_type; - subprog = psp_dir_valid_entries[i].subprog; - break; - } + /* Special handling for AB bootloader */ + if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { + if (cb_config->have_whitelist) + tmp = "PSPBTLDR_AB_FILE"; + else + return 1; } - if (should_skip_entry(fw_name, fw_type, cb_config)) { - fw_type = AMD_FW_SKIP; + + if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) { + if (cb_config->have_whitelist) + return 1; } + fw_name = tmp; + /* Search and fill the filename */ psp_tableptr = &amd_psp_fw_table[0]; - if (fw_type != AMD_FW_SKIP && fw_type != AMD_FW_INVALID) { - while (psp_tableptr->type != AMD_FW_INVALID) { - /* instance are not used in PSP table */ - if (psp_tableptr->type == fw_type && psp_tableptr->subprog == subprog) { + while (psp_tableptr->type != AMD_FW_INVALID) { + if (psp_tableptr->fw_name && + strcmp(fw_name, psp_tableptr->fw_name) == 0) { + fw_type = psp_tableptr->type; + if (!should_skip_entry(fw_type, cb_config)) { psp_tableptr->filename = filename; SET_LEVEL(psp_tableptr, level_to_set, PSP); - break; } - psp_tableptr++; + break; } + psp_tableptr++; } + if (fw_type == AMD_FW_INVALID) return 0; else -- To view, visit https://review.coreboot.org/c/coreboot/+/59584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I552240e53fa0e2f8bef5026e007c8b54458bd656 Gerrit-Change-Number: 59584 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: amdfwtool: replace strcmp to switch-case
by Kangheui Won (Code Review) 23 Nov '21

23 Nov '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59583 ) Change subject: amdfwtool: replace strcmp to switch-case ...................................................................... amdfwtool: replace strcmp to switch-case Since we have separate function for filename to fw_type conversion, when we determine whether we should include the firmware or not we have fw_type. Replace strcmp in if-else to switch-case so it looks more clear. However PSPBTLDR_WL_FILE and PSPBTLDR_AB_FILE have same fw_type so we should use strmp for them. BUG=b:206909680 TEST=build guybrush and confirm amdfw and coreboot.rom are identical Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Icf9f3465a36d83cf79f9f4bd1ec824b546a71aaf --- M util/amdfwtool/data_parse.c 1 file changed, 30 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59583/1 diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index e1b6db9..25e739a 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -157,6 +157,34 @@ {"PSPBTLDR_AB_FILE", AMD_FW_PSP_BOOTLOADER_AB, 0} }; +static bool should_skip_entry(char *fw_name, amd_fw_type fw_type, + amd_cb_config *cb_config) +{ + switch (fw_type) { + case AMD_FW_PSP_SECURED_DEBUG: + case AMD_DEBUG_UNLOCK: + return !(cb_config->unlock_secure); + case AMD_FW_PSP_SECURED_OS: + case AMD_FW_PSP_TRUSTLETS: + case AMD_FW_PSP_TRUSTLETKEY: + return !(cb_config->use_secureos); + case AMD_MP2_FW: + return !(cb_config->load_mp2_fw); + case AMD_S0I3_DRIVER: + return !(cb_config->s0i3); + case AMD_FW_PSP_BOOTLOADER_AB: + if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { + return !(cb_config->have_whitelist); + } else { + return (cb_config->have_whitelist); + } + break; + default: + /* default to include */ + return 0; + } +} + static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, char level_to_set, amd_cb_config *cb_config) { @@ -172,39 +200,8 @@ break; } } - if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { - if (!cb_config->have_whitelist) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "PSPSECUREDEBUG_FILE") == 0) { - if (!cb_config->unlock_secure) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { - if (!cb_config->unlock_secure) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "PSPSECUREOS_FILE") == 0) { - if (!cb_config->use_secureos) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { - if (!cb_config->use_secureos) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "TRUSTLETKEY_FILE") == 0) { - if (!cb_config->use_secureos) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "PSP_MP2FW0_FILE") == 0) { - if (!cb_config->load_mp2_fw) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { - if (!cb_config->load_mp2_fw) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { - if (!cb_config->load_mp2_fw) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { - if (!cb_config->s0i3) - fw_type = AMD_FW_SKIP; - } else if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) { - if (cb_config->have_whitelist) - fw_type = AMD_FW_SKIP; + if (should_skip_entry(fw_name, fw_type, cb_config)) { + fw_type = AMD_FW_SKIP; } /* Search and fill the filename */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf9f3465a36d83cf79f9f4bd1ec824b546a71aaf Gerrit-Change-Number: 59583 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: amdfwtool: unify firmware names
by Kangheui Won (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59582 ) Change subject: amdfwtool: unify firmware names ...................................................................... amdfwtool: unify firmware names Among stoneyridge, picasso, cezanne only picasso uses different name for some firmware blobs. Unify them so amdfwtool can handle them in more consistent manner. BUG=b:206909680 TEST=boot on zork Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Idc3329374ec57ffc045b05ae9cb27bf4e735902f --- M src/soc/amd/picasso/fw.cfg M util/amdfwtool/data_parse.c 2 files changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59582/1 diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg index 516af7b..0c89c88 100644 --- a/src/soc/amd/picasso/fw.cfg +++ b/src/soc/amd/picasso/fw.cfg @@ -11,7 +11,7 @@ PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin PSPSECUREOS_FILE psp_os_combined_prod_RV.sbin -PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin +PSPSECUREDEBUG_FILE RavenSecureDebug_PublicKey.bin PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin @@ -27,7 +27,7 @@ PSP_MP2FW1_FILE MP2I2CFWRV2.sbin PSP_MP2FW2_FILE MP2I2CFWPCO.sbin PSP_MP2CFG_FILE MP2FWConfig.sbin -PSP_DRIVERS_FILE drv_sys_prod_RV.sbin +AMD_DRIVER_ENTRIES drv_sys_prod_RV.sbin # BDT PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index fccea94..37e89ac 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -132,9 +132,6 @@ } else if (strcmp(fw_name, "SMUSCS_FILE") == 0) { fw_type = AMD_FW_PSP_SMUSCS; subprog = 0; - } else if (strcmp(fw_name, "PSPSECUREDEBUG_FILE") == 0) { - fw_type = AMD_FW_PSP_SECURED_DEBUG; - subprog = 0; } else if (strcmp(fw_name, "PSP_SMUFW1_SUB0_FILE") == 0) { fw_type = AMD_FW_PSP_SMU_FIRMWARE; subprog = 0; @@ -156,7 +153,7 @@ } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) { fw_type = AMD_FW_PSP_SMU_FIRMWARE2; subprog = 2; - } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { + } else if (strcmp(fw_name, "PSPSECUREDEBUG_FILE") == 0) { if (cb_config->unlock_secure) { fw_type = AMD_FW_PSP_SECURED_DEBUG; subprog = 0; @@ -248,9 +245,6 @@ } else { fw_type = AMD_FW_SKIP; } - } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { - fw_type = AMD_DRIVER_ENTRIES; - subprog = 0; } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { if (cb_config->s0i3) { fw_type = AMD_S0I3_DRIVER; -- To view, visit https://review.coreboot.org/c/coreboot/+/59582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc3329374ec57ffc045b05ae9cb27bf4e735902f Gerrit-Change-Number: 59582 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: remove duplicates
by Kangheui Won (Code Review) 23 Nov '21

23 Nov '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59581 ) Change subject: amdfwtool: remove duplicates ...................................................................... amdfwtool: remove duplicates Remove duplicated condition check and entries from amdfwtool. BUG=b:206909680 TEST=build guybrush and confirm amdfw and coreboot.rom are identical Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I3b86e24ba1c2769985e2864528e4dfcbf3cccc4b --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/data_parse.c 2 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/59581/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index ee360f0..957c81e 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -268,8 +268,6 @@ { .type = AMD_ABL5, .level = PSP_BOTH }, { .type = AMD_ABL6, .level = PSP_BOTH }, { .type = AMD_ABL7, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH }, diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 8f93183..fccea94 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -132,9 +132,6 @@ } else if (strcmp(fw_name, "SMUSCS_FILE") == 0) { fw_type = AMD_FW_PSP_SMUSCS; subprog = 0; - } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { - fw_type = AMD_FW_PSP_TRUSTLETS; - subprog = 0; } else if (strcmp(fw_name, "PSPSECUREDEBUG_FILE") == 0) { fw_type = AMD_FW_PSP_SECURED_DEBUG; subprog = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/59581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b86e24ba1c2769985e2864528e4dfcbf3cccc4b Gerrit-Change-Number: 59581 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: clean up psp fw parsing
by Kangheui Won (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59449 to look at the new patch set (#4). Change subject: amdfwtool: clean up psp fw parsing ...................................................................... amdfwtool: clean up psp fw parsing find_register_fw_filename_psp_dir parses first token from the fw.cfg and find fw_type and subprog for it. However every entries are hard-coded, which makes code to be hard to read and maintain. Make a new lookup table so things are more organized than before. BUG=b:206909680 TEST=build guybrush and confirm amdfw and coreboot.rom are identical Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Id7adb20db7bab73933b457f3449b2d8ce4217b8c --- M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc M util/amdfwtool/data_parse.c 3 files changed, 79 insertions(+), 167 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59449/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7adb20db7bab73933b457f3449b2d8ce4217b8c Gerrit-Change-Number: 59449 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/kano: set power limits for thermal
by YH Lin (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: David Wu. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59091 ) Change subject: mb/google/brya/var/kano: set power limits for thermal ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19 Gerrit-Change-Number: 59091 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 23 Nov 2021 14:59:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750
by Mark Hsieh (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59579 ) Change subject: mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750 ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/59579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05 Gerrit-Change-Number: 59579 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 23 Nov 2021 14:43:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Update thermal table for Gimble
by Mark Hsieh (Code Review) 23 Nov '21

23 Nov '21

Mark Hsieh has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59102 ) Change subject: mb/google/brya/var/gimble: Update thermal table for Gimble ...................................................................... Abandoned The thermal settings is controlled by dptv.dv, so this patch is not needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/59102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9899bf49dfaa63ee96532b5b90464d83e02daeee Gerrit-Change-Number: 59102 Gerrit-PatchSet: 8 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/elkhartlake: Update SA & IGD DIDs Table Update SA table as ...
by Lean Sheng Tan (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: akino.liao(a)intel.com, Rick Lee, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59559 ) Change subject: soc/intel/elkhartlake: Update SA & IGD DIDs Table Update SA table as per latest EDS (Doc no: 601458). Add extra SKUs accordingly. ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59559/comment/74d8438d_0edaf8e9 PS1, Line 7: & IGD remove this. only SA table updated. https://review.coreboot.org/c/coreboot/+/59559/comment/eaaa5532_4db7f648 PS1, Line 8: Update SA table as per latest EDS (Doc no: 601458). please add a line before this. -- To view, visit https://review.coreboot.org/c/coreboot/+/59559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706 Gerrit-Change-Number: 59559 Gerrit-PatchSet: 1 Gerrit-Owner: Rick Lee <rick.lee(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Praveen HP <praveen.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: akino.liao(a)intel.com Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: akino.liao(a)intel.com Gerrit-Attention: Rick Lee <rick.lee(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 14:04:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add mock assert support for unit testing purposes
by Jakub Czapiga (Code Review) 23 Nov '21

23 Nov '21

Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59495 ) Change subject: libpayload: Add mock assert support for unit testing purposes ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59495/comment/49cdb9a5_73ff7ffd PS1, Line 10: passwd > typo Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e4620400f27dbebc57c71bbf2bf9144ca65807f Gerrit-Change-Number: 59495 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 13:59:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021