coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defs
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59595 ) Change subject: soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defs ...................................................................... soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defs De-duplicate the definitions for the pin status bit and use this new definition in both the C and the ACPI code. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552 --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 2 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59595/1 diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 5a13d8d..579ff68 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -159,7 +159,7 @@ { VAL0, 32 } - Local0 = (GPIO_INPUT_VALUE & VAL0) >> GPIO_INPUT_SHIFT + Local0 = (GPIO_PIN_STS & VAL0) >> GPIO_PIN_STS_SHIFT Return (Local0) } diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index ffc90ed..7345dd1 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -54,15 +54,13 @@ #define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) #define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_PIN_STS (1 << 16) +#define GPIO_PIN_STS_SHIFT 16 +#define GPIO_PIN_STS (1 << GPIO_PIN_STS_SHIFT) #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) #define GPIO_PULL_MASK (GPIO_PULLUP_ENABLE | GPIO_PULLDOWN_ENABLE) -#define GPIO_INPUT_SHIFT 16 -#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) - #define GPIO_OUTPUT_SHIFT 22 #define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) #define GPIO_OUTPUT_ENABLE (1 << 23) -- To view, visit https://review.coreboot.org/c/coreboot/+/59595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552 Gerrit-Change-Number: 59595 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defs
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59594 ) Change subject: soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defs ...................................................................... soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defs The GPIO_WAKE_* definitions are the ones that are used in the code, so drop the unused GPIO_*_WAKE_EN definitions for the same bits. Also move the GPIO_WAKE_* definitions to the place the GPIO_*_WAKE_EN ones were before this patch. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I622673cc72107908b525a65212061062f32e13dd --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 7 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/59594/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 3d97250..ffc90ed 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -46,9 +46,13 @@ #define GPIO_INT_ENABLE_STATUS_DELIVERY (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) #define GPIO_INT_ENABLE_MASK (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) -#define GPIO_S0I3_WAKE_EN (1 << 13) -#define GPIO_S3_WAKE_EN (1 << 14) -#define GPIO_S4_S5_WAKE_EN (1 << 15) +#define GPIO_WAKE_S0i3 (1 << 13) +#define GPIO_WAKE_S3 (1 << 14) +#define GPIO_WAKE_S4_S5 (1 << 15) +#define GPIO_WAKE_S0i3_S3 (GPIO_WAKE_S0i3 | GPIO_WAKE_S3) +#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) #define GPIO_PIN_STS (1 << 16) @@ -130,14 +134,6 @@ #define GPIO_DEB_MASK 0xff -#define GPIO_WAKE_S0i3 (1 << 13) -#define GPIO_WAKE_S3 (1 << 14) -#define GPIO_WAKE_S4_S5 (1 << 15) -#define GPIO_WAKE_S0i3_S3 (GPIO_WAKE_S0i3 | GPIO_WAKE_S3) -#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) - /* * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` * Bits that are preserved/untouched: -- To view, visit https://review.coreboot.org/c/coreboot/+/59594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I622673cc72107908b525a65212061062f32e13dd Gerrit-Change-Number: 59594 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: use bit definitions for masks
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59593 ) Change subject: soc/amd/common/block/include/gpio_defs: use bit definitions for masks ...................................................................... soc/amd/common/block/include/gpio_defs: use bit definitions for masks All bits covered by the bit masks GPIO_INT_ENABLE_MASK, GPIO_PULL_MASK, GPIO_STATUS_MASK and GPIO_WAKE_MASK already have definitions in the code so use those instead of magic numbers. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648 --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59593/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 7ca1c00..3d97250 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -44,7 +44,7 @@ #define GPIO_INT_ENABLE_STATUS (1 << 11) #define GPIO_INT_ENABLE_DELIVERY (1 << 12) #define GPIO_INT_ENABLE_STATUS_DELIVERY (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) -#define GPIO_INT_ENABLE_MASK (3 << 11) +#define GPIO_INT_ENABLE_MASK (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) #define GPIO_S0I3_WAKE_EN (1 << 13) #define GPIO_S3_WAKE_EN (1 << 14) @@ -54,7 +54,7 @@ #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) -#define GPIO_PULL_MASK (3 << 20) +#define GPIO_PULL_MASK (GPIO_PULLUP_ENABLE | GPIO_PULLDOWN_ENABLE) #define GPIO_INPUT_SHIFT 16 #define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) @@ -66,7 +66,7 @@ #define GPIO_INT_STATUS (1 << 28) #define GPIO_WAKE_STATUS (1 << 29) -#define GPIO_STATUS_MASK (3 << 28) +#define GPIO_STATUS_MASK (GPIO_INT_STATUS | GPIO_WAKE_STATUS) #define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) #define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE @@ -136,7 +136,7 @@ #define GPIO_WAKE_S0i3_S3 (GPIO_WAKE_S0i3 | GPIO_WAKE_S3) #define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) #define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_MASK (7 << 13) +#define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) /* * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` -- To view, visit https://review.coreboot.org/c/coreboot/+/59593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648 Gerrit-Change-Number: 59593 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: remove unneeded line break
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59592 ) Change subject: soc/amd/common/block/include/gpio_defs: remove unneeded line break ...................................................................... soc/amd/common/block/include/gpio_defs: remove unneeded line break The definitions of GPIO_INT_ENABLE_STATUS_DELIVERY and GPIO_TIMEBASE_62440uS fit into 96 characters, so remove the unneeded line breaks. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7 --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59592/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 793e717..7ca1c00 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -43,8 +43,7 @@ #define GPIO_INT_ENABLE_STATUS (1 << 11) #define GPIO_INT_ENABLE_DELIVERY (1 << 12) -#define GPIO_INT_ENABLE_STATUS_DELIVERY \ - (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) +#define GPIO_INT_ENABLE_STATUS_DELIVERY (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) #define GPIO_INT_ENABLE_MASK (3 << 11) #define GPIO_S0I3_WAKE_EN (1 << 13) @@ -115,8 +114,7 @@ #define GPIO_TIMEBASE_61uS 0 #define GPIO_TIMEBASE_183uS (1 << 4) #define GPIO_TIMEBASE_15560uS (1 << 7) -#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ - GPIO_TIMEBASE_15560uS) +#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | GPIO_TIMEBASE_15560uS) #define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) #define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) #define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) -- To view, visit https://review.coreboot.org/c/coreboot/+/59592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7 Gerrit-Change-Number: 59592 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: drop 8k pullup define
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59591 ) Change subject: soc/amd/common/block/include/gpio_defs: drop 8k pullup define ...................................................................... soc/amd/common/block/include/gpio_defs: drop 8k pullup define The corresponding bit is marked as reserved in all SoCs using this code so drop the define. Also change the definition of GPIO_PULL_MASK to only cover the bits used for the feature. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33 --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/59591/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 757e0f2..793e717 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -52,10 +52,10 @@ #define GPIO_S4_S5_WAKE_EN (1 << 15) #define GPIO_PIN_STS (1 << 16) -#define GPIO_8KPULLUP_SELECT (1 << 19) + #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) -#define GPIO_PULL_MASK (7 << 19) +#define GPIO_PULL_MASK (3 << 20) #define GPIO_INPUT_SHIFT 16 #define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) @@ -72,7 +72,6 @@ #define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) #define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE -#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) #define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE #define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE #define GPIO_PULL_PULL_NONE 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/59591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33 Gerrit-Change-Number: 59591 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: add GPIO IRQ status registers
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: use lower case in hex numbers
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59589 ) Change subject: soc/amd/common/block/include/gpio_defs: use lower case in hex numbers ...................................................................... soc/amd/common/block/include/gpio_defs: use lower case in hex numbers Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icb1c7b243f655225347ba2a78c80e6e8653e8cda --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/59589/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 8545037..db90211 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -3,13 +3,13 @@ #ifndef AMD_BLOCK_GPIO_DEFS_H #define AMD_BLOCK_GPIO_DEFS_H -#define GPIO_MASTER_SWITCH 0xFC +#define GPIO_MASTER_SWITCH 0xfc #define GPIO_MASK_STS_EN BIT(28) #define GPIO_INTERRUPT_EN BIT(30) #define GPIO_WAKE_EN BIT(31) -#define GPIO_WAKE_STAT_0 0x2F0 -#define GPIO_WAKE_STAT_1 0x2F4 +#define GPIO_WAKE_STAT_0 0x2f0 +#define GPIO_WAKE_STAT_1 0x2f4 #define GPIO_PIN_IN (1 << 0) /* for byte access */ #define GPIO_PIN_OUT (1 << 6) /* for byte access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb1c7b243f655225347ba2a78c80e6e8653e8cda Gerrit-Change-Number: 59589 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: add missing PM_ACPI_* bit definitions
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59588 ) Change subject: soc/amd/cezanne: add missing PM_ACPI_* bit definitions ...................................................................... soc/amd/cezanne: add missing PM_ACPI_* bit definitions This part was copied from Picasso but Cezanne has some more bits used so add the definitions now. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b --- M src/soc/amd/cezanne/include/soc/southbridge.h 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/59588/1 diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index b492088..3bba559 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -44,6 +44,7 @@ #define PM_ACPI_DECODE_STD BIT(0) #define PM_ACPI_GLOBAL_EN BIT(1) #define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_SLPBTN_EN_EN BIT(3) #define PM_ACPI_TIMER_EN_EN BIT(4) #define PM_ACPI_MASK_ARB_DIS BIT(6) #define PM_ACPI_BIOS_RLS BIT(7) @@ -51,11 +52,26 @@ #define PM_ACPI_REDUCED_HW_EN BIT(9) #define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10) #define PM_ACPI_S5_LPC_PIN_MODE BIT(11) +#define PM_ACPI_LPC_RST_DIS BIT(12) +#define PM_ACPI_SEL_PWRGD_PAD BIT(13) +#define PM_ACPI_SEL_SMU_THERMTRIP BIT(14) +#define PM_ACPI_SW_S5PWRMUX_OVRD_N BIT(15) +#define PM_ACPI_SW_S5PWRMUX BIT(16) +#define PM_ACPI_EN_SHUTDOWN_MSG BIT(17) +#define PM_ACPI_EN_SYNC_FLOOD BIT(18) +#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19) +#define PM_ACPI_EN_DF_INTRWAKE BIT(20) +#define PM_ACPI_MASK_USB_S5_RST BIT(21) +#define PM_ACPI_USE_RSMU_RESET BIT(22) +#define PM_ACPI_RST_USB_S5 BIT(23) #define PM_ACPI_BLOCK_PCIE_PME BIT(24) #define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_PCIE_WAK_INTR_DIS BIT(26) #define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_ACPI_USE_GATED_ALINK_CLK BIT(30) +#define PM_ACPI_DELAY_GPP_OFF_TIME BIT(31) #define PM_SPI_PAD_PU_PD 0x90 #define PM_ESPI_CS_USE_DATA2 BIT(16) #define PM_LPC_GATING 0xec -- To view, visit https://review.coreboot.org/c/coreboot/+/59588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b Gerrit-Change-Number: 59588 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/acpi: fix reference to main acpi include
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59587 ) Change subject: soc/amd/common/block/include/acpi: fix reference to main acpi include ...................................................................... soc/amd/common/block/include/acpi: fix reference to main acpi include commit e0844636aca974449c7257e846ec816db683d0b9 (acpi: Move ACPI table support out of arch/x86 (2/5)) moved the main acpi header file from arch/x86/include/acpi/acpi.h to include/acpi/acpi.h, so change the comment in here to point to the current location. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5fddd1cd5eefd83816b1c966b5c7edf53eb2486d --- M src/soc/amd/common/block/include/amdblocks/acpi.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/59587/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 550b7d7..e87fcdb 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -12,7 +12,7 @@ #define MMIO_ACPI_PM1_STS 0x00 #define MMIO_ACPI_PM1_EN 0x02 #define MMIO_ACPI_PM1_CNT_BLK 0x04 - /* sleep types defined in arch/x86/include/acpi/acpi.h */ + /* sleep types defined in include/acpi/acpi.h */ #define ACPI_PM1_CNT_SCIEN BIT(0) #define MMIO_ACPI_PM_TMR_BLK 0x08 #define MMIO_ACPI_CPU_CONTROL 0x0c -- To view, visit https://review.coreboot.org/c/coreboot/+/59587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fddd1cd5eefd83816b1c966b5c7edf53eb2486d Gerrit-Change-Number: 59587 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso,stoneyridge/acpi: use define for RTC_DATE_ALARM
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59586 ) Change subject: soc/amd/picasso,stoneyridge/acpi: use define for RTC_DATE_ALARM ...................................................................... soc/amd/picasso,stoneyridge/acpi: use define for RTC_DATE_ALARM Cezanne already uses a define for this and it's better to define and use constants instead of magic values. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifa4b3b3cdb161670128b284a3396fc5a85545608 --- M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/include/soc/acpi.h 4 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59586/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index c0808d9..a90cbcf 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -92,7 +92,7 @@ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0x0d; + fadt->day_alrm = RTC_DATE_ALARM; fadt->mon_alrm = 0; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 804b27c..2087690 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -8,6 +8,9 @@ #include <device/device.h> #include <stdint.h> +/* RTC Registers */ +#define RTC_DATE_ALARM 0x0d + uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index b2de89e..918ba5e 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -84,7 +84,7 @@ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0x0d; + fadt->day_alrm = RTC_DATE_ALARM; fadt->mon_alrm = 0; /* Not supported */ fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index f0c35c0..21ffd5f 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -12,6 +12,9 @@ #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) #endif +/* RTC Registers */ +#define RTC_DATE_ALARM 0x0d + const char *soc_acpi_name(const struct device *dev); #endif /* AMD_STONEYRIDGE_ACPI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa4b3b3cdb161670128b284a3396fc5a85545608 Gerrit-Change-Number: 59586 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021