coreboot-gerrit November 2021

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Change in coreboot[master]: guybrush: add RO_GSCVD area to FMAP
by Julius Werner (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Hung-Te Lin, Vadim Bendebury, Furquan Shaikh, Mathew King, Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57864 ) Change subject: guybrush: add RO_GSCVD area to FMAP ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/57864/comment/48167bee_c8b7ff50 PS1, Line 29: RO_GSCVD 8K > I thing RO_GSCVD should be part of the RO section, and should be updated only if WP is disabled and the RO is actually updated. That has nothing to do with RO_SECTION though, that's just WP_RO. RO_SECTION is used among other things to calculate the RO firmware hash encoded in the HWID. For these purposes, I think it is cleaner for RO_GSCVD to be outside of RO_SECTION (the RO_SECTION hash is only supposed to change when the firmware behavior itself changes, not other metadata describing it). -- To view, visit https://review.coreboot.org/c/coreboot/+/57864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01 Gerrit-Change-Number: 57864 Gerrit-PatchSet: 1 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 21:18:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Vadim Bendebury <vbendeb(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/i2c: Add sx9360 driver
by build bot (Jenkins) (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: SH Kim. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59608 ) Change subject: driver/i2c: Add sx9360 driver ...................................................................... Patch Set 1: (3 comments) File src/drivers/i2c/sx9360/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134155): https://review.coreboot.org/c/coreboot/+/59608/comment/642bc5d6_20e74499 PS1, Line 31: uint32_t proxraw_strength; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134155): https://review.coreboot.org/c/coreboot/+/59608/comment/9a14b342_b4bd7348 PS1, Line 34: uint32_t avg_pos_strength; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134155): https://review.coreboot.org/c/coreboot/+/59608/comment/b051b3e9_69016971 PS1, Line 37: uint32_t resolution; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516 Gerrit-Change-Number: 59608 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Comment-Date: Tue, 23 Nov 2021 20:10:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Add SAR sensor for bugzzy
by Gwendal Grignou (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: SH Kim. Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59609 to review the following change. Change subject: mb/google/dedede: Add SAR sensor for bugzzy ...................................................................... mb/google/dedede: Add SAR sensor for bugzzy Present 2 SX9360 SAR sensor for bugzzy. Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/bugzzy/gpio.c M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb 6 files changed, 45 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59609/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index f638765..539d31a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit f638765f17cdca735b69229f4f0479562bcb7526 +Subproject commit 539d31ab9ea89084fa5edf7cc9ac3122786d5454 diff --git a/3rdparty/blobs b/3rdparty/blobs index b8e3eaf..fe7040a 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit b8e3eaf7501aaa234e93a4a305bf711cf34bb0ad +Subproject commit fe7040a278642dc3d28e20eb7e7866cb6e2ac2ac diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 3f97690..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 3f97690f0da8011f52209b232450a1e5c4f2e1f6 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 64fca47..03d64a2 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -7,6 +7,7 @@ select DRIVERS_I2C_GPIO_MUX select DRIVERS_I2C_HID select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9360 select DRIVERS_INTEL_DPTF select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI diff --git a/src/mainboard/google/dedede/variants/bugzzy/gpio.c b/src/mainboard/google/dedede/variants/bugzzy/gpio.c index a218c5e..2242eaf 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/gpio.c +++ b/src/mainboard/google/dedede/variants/bugzzy/gpio.c @@ -46,6 +46,10 @@ PAD_NC(GPP_E0, NONE), /* E1 : EMR_RESET_L */ PAD_CFG_GPO(GPP_E1, 0, DEEP), + /* E10 : LTE_SAR_SENSOR_INT */ + PAD_CFG_GPI_APIC(GPP_E10, NONE, PLTRST, LEVEL, NONE), + /* E11 : WIFI_SAR_SENSOR_INT */ + PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, NONE), /* E13 : DDI0_DDC_SCL */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* E14 : DDI0_DDC_SDA */ diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index de1e46d..c64fd50 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -42,6 +42,15 @@ register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -51,10 +60,11 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | + #| I2C1 | Digitizer, P-sensor(LTE) | #| I2C2 | Touchscreen | #| I2C3 | Camera | #| I2C4 | Audio | + #| I2C5 | P-sensor(Wifi) | #+-------------------+---------------------------+ register "common_soc_config" = "{ .panel_orientation = LB_FB_ORIENTATION_RIGHT_UP, @@ -87,6 +97,11 @@ .rise_time_ns = 175, .fall_time_ns = 8, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 88, + .fall_time_ns = 8, + }, }" device domain 0 on device pci 04.0 on @@ -206,13 +221,22 @@ register "hid_desc_reg_offset" = "0x1" device i2c 0x09 on end end + chip drivers/i2c/sx9360 + register "desc" = ""SAR Proximity Sensor - LTE"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E10_IRQ)" + register "uid" = "1" + register "proxraw_strength" = "2" + register "avg_pos_strength" = "16" + register "resolution" = "1024" + device i2c 28 on end + end end # I2C #1 device pci 15.2 on chip drivers/i2c/hid register "generic.hid" = ""HX121A"" register "generic.desc" = ""HX Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" - register "generic.probed" = "1" + #register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "2" @@ -311,6 +335,17 @@ device i2c 1a on end end end #I2C 4 + device pci 19.1 on + chip drivers/i2c/sx9360 + register "desc" = ""SAR Proximity Sensor - Wifi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + register "uid" = "2" + register "proxraw_strength" = "2" + register "avg_pos_strength" = "16" + register "resolution" = "1024" + device i2c 28 on end + end + end #I2C 5 device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98360A"" -- To view, visit https://review.coreboot.org/c/coreboot/+/59609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b Gerrit-Change-Number: 59609 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: driver/i2c: Add sx9360 driver
by Gwendal Grignou (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: SH Kim. Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59608 to review the following change. Change subject: driver/i2c: Add sx9360 driver ...................................................................... driver/i2c: Add sx9360 driver Add driver for setting up Semtech sx9360 SAR sensor. Registers are documented in the kernel tree: Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516 --- A src/drivers/i2c/sx9360/Kconfig A src/drivers/i2c/sx9360/Makefile.inc A src/drivers/i2c/sx9360/chip.h A src/drivers/i2c/sx9360/sx9360.c 4 files changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59608/1 diff --git a/src/drivers/i2c/sx9360/Kconfig b/src/drivers/i2c/sx9360/Kconfig new file mode 100644 index 0000000..ea28564 --- /dev/null +++ b/src/drivers/i2c/sx9360/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_I2C_SX9360 + bool + default n + depends on HAVE_ACPI_TABLES + help + Board has a Semtech SX9360 proximity sensor. diff --git a/src/drivers/i2c/sx9360/Makefile.inc b/src/drivers/i2c/sx9360/Makefile.inc new file mode 100644 index 0000000..695bb52 --- /dev/null +++ b/src/drivers/i2c/sx9360/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_SX9360) += sx9360.c diff --git a/src/drivers/i2c/sx9360/chip.h b/src/drivers/i2c/sx9360/chip.h new file mode 100644 index 0000000..3b928b0 --- /dev/null +++ b/src/drivers/i2c/sx9360/chip.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_I2C_SX9360_CHIP_H__ +#define __DRIVERS_I2C_SX9360_CHIP_H__ + +#include <acpi/acpi_device.h> +#include <device/i2c_simple.h> + +struct drivers_i2c_sx9360_config { + /* Device Description */ + const char *desc; + + /* ACPI _UID */ + unsigned int uid; + + /* Bus speed in Hz, default is I2C_SPEED_FAST */ + enum i2c_speed speed; + + /* Use GPIO-based interrupt instead of IO-APIC */ + struct acpi_gpio irq_gpio; + + /* IO-APIC interrupt */ + struct acpi_irq irq; + + /* + * Registers definition in the kernel source tree at: + * Documentation/devicetree/bindings/iio/proximity/semtech,sx9310.yaml + */ + + /* Raw Proximity filter strength: When not set, disabled. */ + uint32_t proxraw_strength; + + /* Average Proximity filter strength: When not set, disabled. */ + uint32_t avg_pos_strength; + + /* Capacitance measure resolution. Driver default: 128. */ + uint32_t resolution; +}; + +#endif /* __DRIVERS_I2C_SX9360_CHIP_H__ */ diff --git a/src/drivers/i2c/sx9360/sx9360.c b/src/drivers/i2c/sx9360/sx9360.c new file mode 100644 index 0000000..b06882a --- /dev/null +++ b/src/drivers/i2c/sx9360/sx9360.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/i2c_simple.h> +#include <device/device.h> +#include <device/path.h> +#include <string.h> +#include "chip.h" + +#define I2C_SX9360_ACPI_ID "STH9360" +#define I2C_SX9360_CHIP_NAME "Semtech SX9360" + +#define REGISTER(NAME) acpi_dp_add_integer(dsd, \ + I2C_SX9360_ACPI_ID "," #NAME, \ + config->NAME) + +static void i2c_sx9360_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_sx9360_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dsd; + + if (!scope || !config) + return; + + if (config->speed) + i2c.speed = config->speed; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", I2C_SX9360_ACPI_ID); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + if (config->irq_gpio.pin_count) + acpi_device_write_gpio(&config->irq_gpio); + else + acpi_device_write_interrupt(&config->irq); + + acpigen_write_resourcetemplate_footer(); + + /* DSD */ + dsd = acpi_dp_new_table("_DSD"); + + /* + * Format describe in linux kernel documentation. See + * https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/… + */ + acpi_dp_add_integer(dsd, "semtech,proxraw-strength", + config->proxraw_strength); + acpi_dp_add_integer(dsd, "semtech,avg-pos-strength", + config->avg_pos_strength); + acpi_dp_add_integer(dsd, "semtech,resolution", + config->resolution); + + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + config->desc ? : dev->chip_ops->name, dev_path(dev)); +} + +#undef REGISTER + +static const char *i2c_sx9360_acpi_name(const struct device *dev) +{ + static char name[5]; + + snprintf(name, sizeof(name), "SX%02.2X", dev->path.i2c.device); + return name; +} + +static struct device_operations i2c_sx9360_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = i2c_sx9360_acpi_name, + .acpi_fill_ssdt = i2c_sx9360_fill_ssdt, +}; + +static void i2c_sx9360_enable(struct device *dev) +{ + struct drivers_i2c_sx9360_config *config = dev->chip_info; + + if (!config) { + dev->enabled = 0; + return; + } + + dev->ops = &i2c_sx9360_ops; + + if (config->desc) + dev->name = config->desc; +} + +struct chip_operations drivers_i2c_sx9360_ops = { + CHIP_NAME(I2C_SX9360_CHIP_NAME) + .enable_dev = i2c_sx9360_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/59608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516 Gerrit-Change-Number: 59608 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Add util/kconfig/Makefile.real to nocompile list
by Martin Roth (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Patrick Georgi. Hello Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59607 to look at the new patch set (#2). Change subject: Makefile: Add util/kconfig/Makefile.real to nocompile list ...................................................................... Makefile: Add util/kconfig/Makefile.real to nocompile list Messages shown with the $(info Make command could be shown twice because the entire Makefile stack was evaluated twice at MAKELEVEL 0. The first time was to generate the build/util/kconfig/Makefile.real file. The second time was to do the rest of the build. Adding the kconfig Makefile.real file to the nocompile list prevents all the rest of the coreboot makefiles from being read in during that first step, which prevents the messages from being printed twice. You can see this behavior by running "make clean; make -d" and searching for the text: "Successfully remade target file 'build/util/kconfig/Makefile.real'." This breaks when the build target is 'tools', so add an exception for just that target. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If29c3a84c7c82ea099ef9610f4ecaa599f0d8649 --- M Makefile 1 file changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59607/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If29c3a84c7c82ea099ef9610f4ecaa599f0d8649 Gerrit-Change-Number: 59607 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Makefile: Add util/kconfig/Makefile.real to nocompile list
by Martin Roth (Code Review) 23 Nov '21

23 Nov '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59607 ) Change subject: Makefile: Add util/kconfig/Makefile.real to nocompile list ...................................................................... Makefile: Add util/kconfig/Makefile.real to nocompile list Messages shown with the $(info Make command could be shown twice because the entire Makefile stack was evaluated twice at MAKELEVEL 0. The first time was to generate the build/util/kconfig/Makefile.real file. The second time was to do the rest of the build. Adding the kconfig Makefile.real file to the nocompile list prevents all the rest of the coreboot makefiles from being read in during that first step, which prevents the messages from being printed twice. You can see this behavior by running "make clean; make -d" and searching for the text: "Successfully remade target file 'build/util/kconfig/Makefile.real'." Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If29c3a84c7c82ea099ef9610f4ecaa599f0d8649 --- M Makefile 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59607/1 diff --git a/Makefile b/Makefile index c148c11..ba20111 100644 --- a/Makefile +++ b/Makefile @@ -42,6 +42,7 @@ KCONFIG_NEGATIVES := 1 KCONFIG_STRICT := 1 KCONFIG_PACKAGE := CB.Config +KCONFIG_MAKEFILE_REAL ?= $(obj)/util/kconfig/Makefile.real COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE @@ -55,6 +56,7 @@ KBUILD_DEFCONFIG := configs/defconfig UNAME_RELEASE := $(shell uname -r) HAVE_DOTCONFIG := $(wildcard $(DOTCONFIG)) +HAVE_KCONFIG_MAKEFILE_REAL := $(wildcard $(KCONFIG_MAKEFILE_REAL)) MAKEFLAGS += -rR --no-print-directory # Make is silent per default, but 'make V=1' will show all compiler calls. @@ -103,14 +105,18 @@ # Order _does_ matter for pattern rules. include $(srck)/Makefile.inc -# Three cases where we don't need fully populated $(obj) lists: +# Four cases where we don't need fully populated $(obj) lists: # 1. when no .config exists -# 2. when make config (in any flavour) is run -# 3. when make distclean is run +# 2. When no $(obj)/util/kconfig/Makefile.real exists +# 3. when make config (in any flavour) is run +# 4. when make distclean is run # Don't waste time on reading all Makefile.incs in these cases ifeq ($(strip $(HAVE_DOTCONFIG)),) NOCOMPILE:=1 endif +ifeq ($(strip $(HAVE_KCONFIG_MAKEFILE_REAL)),) +NOCOMPILE:=1 +endif ifneq ($(MAKECMDGOALS),) ifneq ($(filter %config %clean cross% clang iasl lint% help% what-jenkins-does,$(MAKECMDGOALS)),) NOCOMPILE:=1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If29c3a84c7c82ea099ef9610f4ecaa599f0d8649 Gerrit-Change-Number: 59607 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*: PSP verstage minbuild
by build bot (Jenkins) (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59585 ) Change subject: soc/amd/*: PSP verstage minbuild ...................................................................... Patch Set 2: (2 comments) File src/soc/amd/common/psp_verstage/psp_verstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134152): https://review.coreboot.org/c/coreboot/+/59585/comment/0c7d9a08_14378fab PS2, Line 258: memset(_transfer_buffer,0,buffer_size); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134152): https://review.coreboot.org/c/coreboot/+/59585/comment/08ff5e50_90602dda PS2, Line 258: memset(_transfer_buffer,0,buffer_size); space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/59585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie506193d21207ecabe65158e84dc02eec1cf5b26 Gerrit-Change-Number: 59585 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 23 Nov 2021 18:35:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*: PSP verstage minbuild
by Martin Roth (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59585 to look at the new patch set (#2). Change subject: soc/amd/*: PSP verstage minbuild ...................................................................... soc/amd/*: PSP verstage minbuild The PSP that is supplied for Picasso AMD-based chromebooks currently requires a psp_verstage to boot. This supplies a minimal psp verstage that does the initialization that's normally done there, then exits without doing any verification. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ie506193d21207ecabe65158e84dc02eec1cf5b26 --- M src/arch/x86/car.ld M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/Kconfig M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 6 files changed, 72 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59585/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie506193d21207ecabe65158e84dc02eec1cf5b26 Gerrit-Change-Number: 59585 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/U-Boot: Enable the frame buffer
by Simon Glass (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Martin Roth, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59605 to look at the new patch set (#3). Change subject: payloads/U-Boot: Enable the frame buffer ...................................................................... payloads/U-Boot: Enable the frame buffer U-Boot normally runs with a display if available. Enable this option so that the display shows if U-Boot supports it. Use 'select' rather than 'imply' since the CI complains. Signed-off-by: Simon Glass <sjg(a)chromium.org> Change-Id: Ie5684c6ead30076689f43034675ff9f3531970fe --- M payloads/external/U-Boot/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59605/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5684c6ead30076689f43034675ff9f3531970fe Gerrit-Change-Number: 59605 Gerrit-PatchSet: 3 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/U-Boot: Move to v2021.10
by Simon Glass (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Martin Roth, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59606 to look at the new patch set (#2). Change subject: payloads/U-Boot: Move to v2021.10 ...................................................................... payloads/U-Boot: Move to v2021.10 Move to building the latest U-Boot. Signed-off-by: Simon Glass <sjg(a)chromium.org> Change-Id: I33fcfc3135e55d16b0dcd8135217bd5adcef2099 --- M payloads/external/U-Boot/Makefile 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/59606/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33fcfc3135e55d16b0dcd8135217bd5adcef2099 Gerrit-Change-Number: 59606 Gerrit-PatchSet: 2 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021