Xuxin Xiong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58994 )
Change subject: google/trogdor: Update the power on sequence of ps8640
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58994/comment/6eb84be5_48dd6325
PS3, Line 2: xuxinxiong
> Got it, Thanks!
Done
https://review.coreboot.org/c/coreboot/+/58994/comment/f090995a_ea332b0c
PS3, Line 17: xuxinxiong
> Got it, Thanks!
Done
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Hou-hsun Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59576 )
Change subject: mb/google/brya/var/brask: Set PL and PsysPL
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/brya/variants/brask/ramstage.c:
https://review.coreboot.org/c/coreboot/+/59576/comment/afc7e4b3_2d2449d1
PS1, Line 18: { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 5000, 45000, 80000, 80000, 159000 },
Those PL2/PL4 values look like coming from baseline config. Have you decided to use baseline or performance line config for Brask?
Btw, from ADL MoW WW46 (doc#626774), the 442 45W SKU (which maps to PCI_DEVICE_ID_INTEL_ADL_P_ID_1) had some PD optimization relaxation. The PL2 is down to 95W, and PL4 is down to 125W, please update the settings for this SKU accordingly.
https://review.coreboot.org/c/coreboot/+/59576/comment/71ad9937_f9f45700
PS1, Line 23: { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135, 257 },
If the psys_pmax_power is not used at all, I think it's better to remove it to avoid confusion.
The psys_pmax calculation is done by psys_imax_ma * volts_mv in variant_update_psys_power_limits(). Is my understanding correct?
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Change subject: mb/google/brya/var/vell: update memory settings
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/google/brya/variants/vell/memory.c:
https://review.coreboot.org/c/coreboot/+/59334/comment/5b9fd38b_cf723c13
PS5, Line 7: __weak
remove if you want to override
https://review.coreboot.org/c/coreboot/+/59334/comment/dfd315dc_a8cc96db
PS5, Line 26: __weak
remove if you want to override
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Change subject: mb/google/brya/variants/primus: update gpios for power consumption
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/google/brya/variants/primus/variant.c:
https://review.coreboot.org/c/coreboot/+/59563/comment/9f9f37a0_c202f324
PS4, Line 46: get_sku_and_set_gpio
> suggestion: […]
Done
https://review.coreboot.org/c/coreboot/+/59563/comment/cb729f30_c9d6a709
PS4, Line 48: int sku = gpio_get(GPP_T2);
:
: if (sku == 1)
> nit: as fars as I can tell, this GPIO is just stuffed on boards with the eMMC, so let's avoid the te […]
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: merge lookup table to psp fw table
......................................................................
amdfwtool: merge lookup table to psp fw table
Merge psp_dir_valid_entries into amd_psp_fw_table. PSPBTLDR_WL_FILE and
PSPBTLDR_AB_FILE needs additional logic since both points to the same
firmware entry and which one to include depends on commandline option.
BUG=b:206909680
TEST=build guybrush and confirm amdfw and coreboot.rom are identical
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Change-Id: I552240e53fa0e2f8bef5026e007c8b54458bd656
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 116 insertions(+), 127 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/59584/2
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Change subject: amdfwtool: replace strcmp to switch-case
......................................................................
amdfwtool: replace strcmp to switch-case
Since we have separate function for filename to fw_type conversion, when
we determine whether we should include the firmware or not we have
fw_type.
Replace strcmp in if-else to switch-case so it looks more clear. However
PSPBTLDR_WL_FILE and PSPBTLDR_AB_FILE have same fw_type so we should use
strmp for them.
BUG=b:206909680
TEST=build guybrush and confirm amdfw and coreboot.rom are identical
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Change-Id: Icf9f3465a36d83cf79f9f4bd1ec824b546a71aaf
---
M util/amdfwtool/data_parse.c
1 file changed, 29 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59583/2
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Change subject: guybrush: add RO_GSCVD area to FMAP
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Guybrush leads should give the +2, but looks good to me now. (Not sure who that is... […]
yes, I think we should add these to all boards in dev, it won't hurt to allocate 8K in megabytes of flash.
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Change subject: src/mb/brya: Enable crashlog on brya0
......................................................................
src/mb/brya: Enable crashlog on brya0
Enabling crashlog helps partners to debug hang issues efficiently.
BUG=b:195327879
TEST=Found BERT table is created and the tcss function is ok in
depthcharge. Warm/cold/suspend_stress test pass 50 cycles on gimble
Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9
Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59486/7
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